ISO 11898-5:2007 全文(低功耗模式)

标准信息:Road vehicles — CAN — Part 5: High-speed medium access unit with low-power mode,ISO 2007 年发布(编号 40399);后并入 ISO 11898-2:2016。 全文定位:完整正文站内查阅,章节结构与表格已保留(自动提取整理)。

← 返回标准查阅 INTERNATIONAL STANDARD ISO 11898-5 First edition 2007-06-15 Road vehicles—Controller area network (CAN) 一 Part 5: High-speed medium access unit with low-power mode Véhicules routiers—Gestionnaire de réseau de communication (CAN)— Partie 5:Unité d’acces au médium haute vitesse avec mode de puissance réduite Reference number ISO 11898-5:2007(E) ◎ ISO 2007 ISO 11898-5:2007(E) Contents Page ◎ISO 2007-All rights reserved iii ISO 11898-5:2007(E) Foreword ISO(the International Organization for Standardization)is a worldwide federation of national standards bodies (ISO member bodies).The work of preparing International Standards is normally carried out through ISO technical committees.Each member body interested in a subject for which a technical committee has been established has the right to be represented on that committee.International organizations,governmental and non-governmental,in liaison with ISO,also take part in the work.ISO collaborates closely with the International Electrotechnical Commission(IEC)on all matters of electrotechnical standardization. International Standards are drafted in accordance with the rules given in the ISO/IEC Directives,Part 2. The main task of technical committees is to prepare International Standards.Draft International Standards adopted by the technical committees are circulated to the member bodies for voting.Publication as an International Standard requires approval by at least 75%of the member bodies casting a vote. Attention is drawn to the possibility that some of the elements of this document may be the subject of patent rights.ISO shall not be held responsible for identifying any or all such patent rights. ISO 11898-5 was prepared by Technical Committee ISO/TC 22,Road vehicles,Subcommittee SC 3, Electrical and electronic equipment. ISO 11898 consists of the following parts,under the general title Road vehicles —Controller area network (CAN): —Part 1:Data link layer and physical signalling —Part 2:High-speed medium access unit —Part 3:Low-speed,fault-tolerant,medium-dependent interface —Part 4:Time-triggered communication —Part 5:High-speed medium access unit with low-power mode iv ◎ ISO 2007-All rights reserved ISO 11898-5:2007(E) Introduction ISO 11898 was first published as one document in 1993.It covered the CAN data link layer as well as the high-speed physical layer. In the reviewed and restructured ISO 11898 series: —Part 1 describes the data link layer including the logical link control (LLC)sub layer and the medium access control(MAC)sub layer as wellas the physical signalling(PLS)sub layer; —Part 2 defines the high-speed medium access unit(MAU); —Part 3 defines the low-speed fault-tolerant medium access unit(MAU); —Part 4 defines the time-triggered communication; —Part 5 defines the power modes of the high-speed medium access unit(MAU). ISO 11898-1 and ISO 11898-2 have been cancelled and replaced ISO 11898:1993. INTERNATIONAL STANDARD ISO 11898-5:2007(E) Road vehicles—Controller area network (CAN) 一 Part 5: High-speed medium access unit with low-power mode

1 Scope

This part of ISO 11898 specifies the CAN physical layer for transmission rates up to 1 Mbit/s for use within road vehicles.It describes the medium access unit functions as well as some medium dependent interface features according to ISO/IEC 8802-2. This part of ISO 11898 represents an extension of ISO 11898-2,dealing with new functionality for systems requiring low-power consumption features while there is no active bus communication. Physical layer implementations according to this part of ISO 11898 are compliant with all parameters of ISO 11898-2,but are defined differently within this part of ISO 11898.Implementations according to this part of ISO 11898 and ISO 11898-2 are interoperable and can be used at the same time within one network.

2 Normative references

The following referenced documents are indispensable for the application of this document.For dated references,only the edition cited applies.For undated references,the latest edition of the referenced document (including any amendments)applies. ISO 7637-3,Road vehicles —Electrical disturbances from conduction and coupling —Part 3:Electrical transient transmission by capacitive and inductive coupling via lines other than supply lines ISO 11898-2:2003,Road vehicles —Controller area network (CAN)—Part 2:High-speed medium access unit

3 Terms and definitions

For the purposes of this document,the terms and definitions given in ISO 11898-2 and the following apply. 3.1 VCC 〈CAN node>supply voltage of the physical layer used for the bus receiver,transmitter and optional split termination voltage Vsplit during normal mode NOTE Typical voltage of VCC is 5V. 3.2 split termination voltage Vsplit 〈CAN node)output voltage of split termination support output relative to ground signal of the module(GND) ◎ISO 2007-All rights reserved 1 ISO 11898-5:2007(E) 3.3 propagation time tProp 〈CAN node)signal propagation time measured from an edge at transmit data(TXD)input to the corresponding edge on receive data(RXD)output of the MAU 3.4 wake-up filter time 〈CAN node)duration of a dominant signal on the bus lines CAN_H and CAN_L for forcing a wake-up to the CAN NODE 3.5 wake-up pattern 〈CAN node)one or multiple consecutive dominant bus levels for at least twake,each separated by a recessive bus level NOTE Figures within this part of ISO 11898 are using arrows as following:voltages+→-;currents flowing from the positive to the negative pole.

4 Symbols and abbreviated terms

For the purposes of this document,the symbols and abbreviated terms given in ISO 11898-2 apply.

5 Functional description of medium access unit(MAU)with low-power mode

5.1 General

The following description is valid for a two-wire differential bus.The values of the voltage levels,the resistances and the capacitances as well as the termination network are described in Clause 7.

5.2 Physical medium attachment sub layer specification

5.2.1 General

As shown in Figure 1 the bus line is terminated by termination network A and termination network B.These terminations are intended to suppress reflections. Besides this reflection-optimized termination structure,centralized single terminations are possible at limited bit rates and topologies. Figure 1—Suggested electrical interconnection

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ISO 11898-5:2007(E) Two different termination models are recommended within the high-speed medium access unit according to Figures 1 and 2: —termination with a single resistor between CAN_H and CAN_L,and —split termination dividing the single resistor into two resistors with the same value in series connection, while the centre tap is connected to a grounding capacitor and optionally to a dedicated split supply. CAN_H- R CAN_L 一 CAN_H 1 Split (optional) CAN_L CAN_H- C Split CAN_L 一 12 12 CAN_H 1 Split (optional) CAN_L Key

1 physical layer

Figure 2—Termination variants,single resistor termination and split termination In order to support low-power functionality,two different modes of operation are defined as follows. —Normal mode:The behaviour during normal mode is described within ISO 11898-2. —Low-power mode:Described within this part of ISO 11898.

5.2.2 Bus levels during normal mode

The bus can have one of the two logical states:recessive or dominant(see Figure 3). The bus is in the recessive state if the bus drivers of all CAN nodes are switched off.In this case,the mean bus voltage is generated by the termination and by the high internal resistance of each CAN node’s receiving circuitry.In the recessive state,VCAN_H and VCANLare fixed to a mean voltage level,determined by the bus termination.Vif is less than a maximum threshold.The recessive state is transmitted during bus idle or a recessive bit.Figure 3 illustrates the maximum allowed differential recessive bus voltage.Typically,the differential voltage is about zero volts. Optionally the recessive bus state may become stabilized making use of a dedicated split termination voltage (Vspit).This optional output voltage of physical layer implementations according to this part of ISO 11898 may be optionally connected to the centre tap of the split termination resistors.Whenever the receiver of a physical layer is not actively biasing towards 2,5 V,the optional Vspit shall become floating. A dominant bit is sent to the bus if the bus driver of at least one unit is switched on.This induces a current flow through the terminating resistors,and consequently a differential voltage between the two wires of the bus.A differential voltage greater than a minimum threshold represents the dominant state.The dominant state overwrites the recessive state,and is transmitted during a dominant bit. The dominant and recessive states are detected by transforming the differential voltages of the bus to the corresponding recessive and dominant voltage levels within the receive comparator. During arbitration,various CAN nodes may simultaneously transmit a dominant bit.In this case,Vdiff exceeds the Vdiff seen during a single operation.Single operations means that the bus is driven by one CAN node only. ◎ISO 2007-All rights reserved 3 ISO 11898-5:2007(E)

5.2.3 Bus levels during low-power mode

During low-power mode,the bus drivers are entirely disabled.It is not possible to actively drive a differential level to the bus lines using a physical layer within low-power mode.In contrast to the normal mode behaviour, the bus wires shall be pulled to the ground signal of the module(GND)via the high-ohmic internal input resistors Rin of the receiver.Thus,there is no active VCC supply required defining the bus levels during low- power operation. The optional split termination voltage(Vsplit)is disabled here and shall behave high-ohmic(floating)in order not to pull the bus into a certain direction. From a physical point of view,there are only the two defined operating conditions possible.The normal mode with VCC/2 biasing whenever normal bus communication takes place and low-power mode with GND biasing whenever the system becomes shutdown. Recessive Dominant Recessive Time,t 3 VCC RXD 2 Key

1 normal mode

2 low-power mode

3 simplified transceiver bias implementation

Figure 3—Physical bit representation and simplified bias implementation

5.2.4 Wake-up out of low-power mode

During low-power operation,a physical layer optionally shall monitor the bus lines CAN_H and CAN_L for wake-up events.Implementations supporting this feature shall make use of a differential bus comparator monitoring the bus line.A bus wake-up shall be performed if the bus shows one or multiple consecutive dominant bus levels for at least twake,each separated by a recessive bus level.

5.2.5 Systems with unpowered nodes

In order to allow undisturbed CAN communication in systems,which have a couple of nodes intentionally unpowered(e.g.ignition key controlled modules),while other nodes continue to communicate normally,it is important that these unpowered nodes affect the bus levels as little as possible.This requires that transceivers,which are temporarily unpowered,show a lowest possible leakage current to the bus lines inside the still communicating system.The lower the leakage current in the unpowered case,the better the system performance in the permanently supplied part of the network. Depending on the target application(permanently supplied or temporarily unsupplied)the maximum leakage parameter according to Table 4 can be tolerated(permanently supplied nodes)or should be reduced as far as possible (temporarily unsupplied nodes). NOTE In contrast to a low-power mode,where the device is still supplied,unpowered means a physical disconnection from the power supply.

6 Conformance tests

6.1 General

All conformance tests for normal mode of operation are specified in ISO 11898-2.Besides these tests,some tests are added dealing with the optional Vsplit functionality and the low-power mode behaviour. The figures and the formulae shown within this clause indicate the principles of how the electrical parameters specified in Clause 7 should be verified.

6.2 Vsplit output function

6.2.1 General

Vspit is an optional output voltage supporting recessive bus stabilization.When this function is implemented, the behaviour of that output shall be measured as shown within the following clauses.

6.2.2 Vsplit during normal mode

The optional output Vsplit delivers an output voltage of VCC/2 during normal mode. According to Table 6,an output current of +500 μA to GND(Figure 4 schematic A)and-500 μA to VCC (Figure 4 schematic B)shall be adjusted with the resistor R,while the output voltage Vsplit shall stay within the limits. In unloaded condition (Figure 4 schematic C),the output voltage shall be checked according to Table 6 using a load resistance of≥1 MΩ . Unloaded ④ Split condition R=5k CANSe R (optional)≥1 MQ (optional) □R=5kΩ V Ground C Figure 4—Measurement of Vsplit during normal mode

6.2.3 Vspit during low-power mode

The optional output Vsplit shall float during low-power mode (see Figure 5).The leakage current is defined in Table 6. ◎ISO 2007-All rights reserved 5 ISO 11898-5:2007(E) A U Split ① Ground Figure 5—Measurement of leakage current Isplitduring low-power mode

6.3 Output voltage during low-power mode

During low-power mode,CAN_H and CAN_L shall be pulled towards GND using the internal input resistor Rin of the bus receiver network (see Figure 6).Voltage levels at CAN_H and CAN_L shall be in accordance with Table 8. CAN_H ECU CAN_L V V Ground- Figure 6—Measurement of VCANLand VCAN_H during low-power mode

6.4 Internal resistance during low-power mode

During low-power mode,CAN_H and CAN_L shall be pulled towards GND with the internal input resistor network (see Figure 7),according to Table 9. CAN_H- ECU CAN_L Ground R. Test ↓ ① )U.Test Figure 7—Measurement of Rinduring low-power mode Applying a voltage UTest to the test circuit allows the calculation of Rin based on the voltage divider defined with RTest as follows:

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ISO 11898-5:2007(E)

6.5 Propagation delay during normal mode

In case of access to the pins RXD [Receive Data (serialized data)]and TXD [Transmit Data(serialized data)] of a physical layer implementation,the signal propagation time shall be measured according to Figure 8. Table 11 specifies the propagation time and defines values for RL,CL,fTxD and CRXD · Figure 8—Measurement of tprop during normal mode

6.6 Wake-up filter time during low-power mode

In order to suppress unwanted wake-up events within physical layers supporting a remote bus wake-up feature,a certain dominant filter time shall be implemented (see Figure 9). The device under test shall not signal a wake-up condition with dominant pulses shorter than twake(min)and shall signal a wake-up condition with dominant pulses longer than twake(max)according to Table 11.Dominant pulses with a length between twake(min)and twake(max).may lead to a wake-up depending on filter spread. According to the target bit rate of the system,the individual time thresholds of an implementation can be adapted,but shall stay within the defined minimum and maximum timings as defined in Table 11. The test shall be performed within the full common mode voltage range as specified in Table 3. RL,UCM,tPulse and I values are defined in Table 11. Figure 9—Measurement of the wake-up filter time during low-power mode

6.7 Bus driver symmetry during normal mode

Due to electromagnetic compatibility(EMC)reasons,the CAN_H and CAN_L driver stage must behave symmetrically,especially during the bit transitions from recessive to dominant and dominant to recessive.An oscilloscope is used to verify that the so-called common mode bus voltage stays within the limits during the recessive bit time,the dominant bit time and the bit transition times,according to Table 5.(See Figure 10.) RL,fTxD and Cspit values are defined in Table 5,and VsYM=VCAN_H+VCAN_L ◎ISO 2007-All rights reserved 7 Figure 10—Measurement of bus driver symmetry VSYM

6.8 Input leakage current,unpowered device

An unpowered device shall not disturb the communication of the residual network.The required maximum leakage currents ICAN_H and ICAN_as well as UBus and Usupply are definedin Table 4.(See Figure 11.) Figure 11—Measurement of input leakage current of an unpowered device

7 Electrical specification of high-speed medium access unit(HS-MAU)

7.1 Physical medium attachment sub layer specification

7.1.1 General

All data given in Tables 1 to 10 are independent of a specific physical layer implementation.The parameters specified in these tables shall be fulfilled throughout the operating temperature range as specified for every individua CAN node.

7.1.2 Bus levels

7.1.2.1 Common mode voltages

The parameters specified in Tables 1 to 6 apply when all CAN nodes are connected to a correctly terminated bus.

7.1.2.2 Disturbance by coupling

The tolerated disturbances of CAN_H and CAN_L by coupling are defined in accordance with ISO 7637-3, test pulses 3a and 3b.

7.1.3 Optional split output level

The optional split out put level is indicated in Table 6. ISO 11898-5:2007(E) Table 1—Bus voltage parameters for reception of recessive state,normal mode

| Parameter | Notation | Unit | min. | Value nom. | max. | Condition | |---|---|---|---|---|---|---| | Common mode bus voltage | VCANH | V | 一 | 2,5 | 12,0 | Measured with respect to the individual ground of each CAN node | | Common mode bus voltage | VCANL | V | -12,0 | 2,5 | 一 | Measured with respect to the individual ground of each CAN node | | Differential bus voltagea | Vdiff | mV | -120 | 0 | 12 | Measured at each CAN node connected to the bus | | a The ifferential bus voltage is determined by the output behaviour of allCAN nodes during the recessive state.Therefore,Vdrif is approximately zero(see Table 8).The minimum value is determined by the requirement that a single bus driver shall be able to represent a dominant bit by a minimum value of Vdiff=1,2V. | a The ifferential bus voltage is determined by the output behaviour of allCAN nodes during the recessive state.Therefore,Vdrif is approximately zero(see Table 8).The minimum value is determined by the requirement that a single bus driver shall be able to represent a dominant bit by a minimum value of Vdiff=1,2V. | a The ifferential bus voltage is determined by the output behaviour of allCAN nodes during the recessive state.Therefore,Vdrif is approximately zero(see Table 8).The minimum value is determined by the requirement that a single bus driver shall be able to represent a dominant bit by a minimum value of Vdiff=1,2V. | a The ifferential bus voltage is determined by the output behaviour of allCAN nodes during the recessive state.Therefore,Vdrif is approximately zero(see Table 8).The minimum value is determined by the requirement that a single bus driver shall be able to represent a dominant bit by a minimum value of Vdiff=1,2V. | a The ifferential bus voltage is determined by the output behaviour of allCAN nodes during the recessive state.Therefore,Vdrif is approximately zero(see Table 8).The minimum value is determined by the requirement that a single bus driver shall be able to represent a dominant bit by a minimum value of Vdiff=1,2V. | a The ifferential bus voltage is determined by the output behaviour of allCAN nodes during the recessive state.Therefore,Vdrif is approximately zero(see Table 8).The minimum value is determined by the requirement that a single bus driver shall be able to represent a dominant bit by a minimum value of Vdiff=1,2V. | a The ifferential bus voltage is determined by the output behaviour of allCAN nodes during the recessive state.Therefore,Vdrif is approximately zero(see Table 8).The minimum value is determined by the requirement that a single bus driver shall be able to represent a dominant bit by a minimum value of Vdiff=1,2V. |

Table 2—Bus voltage parameters for reception of dominant state,normal mode

| Parameterr | Notation | Unit | min. | Value nom. | max. | Condition | |---|---|---|---|---|---|---| | Common mode bus voltage a | VCAN_H | V | 一 | 3,5 | 12,0 | Measured with respect to the individual ground of each CAN node | | Common mode bus voltage a | VCAN_L | V | -12,0 | 1,5 | 一 | Measured with respect to the individual ground of each CAN node | | Differential bus voltage b | Vdiff | V | 1,2 | 2,0 | 3,0 | Measured at each CAN node connected to the bus | | a The minimum value of VCANH is determined by the minimum value of VCANplus the minimum value of Vd.The maximum value of VcAN_is determined by the maximum value of VCAN_Hminus the minimum value of Vdif The bus load increases as CAN nodes are added to the network,by Rdif.Consequently,Vdif decreases.The minimum value of Vaim determines the number of CAN nodes allowed on the bus.The maximum value of Vaif is specified by the upper limit during arbitration. | a The minimum value of VCANH is determined by the minimum value of VCANplus the minimum value of Vd.The maximum value of VcAN_is determined by the maximum value of VCAN_Hminus the minimum value of Vdif The bus load increases as CAN nodes are added to the network,by Rdif.Consequently,Vdif decreases.The minimum value of Vaim determines the number of CAN nodes allowed on the bus.The maximum value of Vaif is specified by the upper limit during arbitration. | a The minimum value of VCANH is determined by the minimum value of VCANplus the minimum value of Vd.The maximum value of VcAN_is determined by the maximum value of VCAN_Hminus the minimum value of Vdif The bus load increases as CAN nodes are added to the network,by Rdif.Consequently,Vdif decreases.The minimum value of Vaim determines the number of CAN nodes allowed on the bus.The maximum value of Vaif is specified by the upper limit during arbitration. | a The minimum value of VCANH is determined by the minimum value of VCANplus the minimum value of Vd.The maximum value of VcAN_is determined by the maximum value of VCAN_Hminus the minimum value of Vdif The bus load increases as CAN nodes are added to the network,by Rdif.Consequently,Vdif decreases.The minimum value of Vaim determines the number of CAN nodes allowed on the bus.The maximum value of Vaif is specified by the upper limit during arbitration. | a The minimum value of VCANH is determined by the minimum value of VCANplus the minimum value of Vd.The maximum value of VcAN_is determined by the maximum value of VCAN_Hminus the minimum value of Vdif The bus load increases as CAN nodes are added to the network,by Rdif.Consequently,Vdif decreases.The minimum value of Vaim determines the number of CAN nodes allowed on the bus.The maximum value of Vaif is specified by the upper limit during arbitration. | a The minimum value of VCANH is determined by the minimum value of VCANplus the minimum value of Vd.The maximum value of VcAN_is determined by the maximum value of VCAN_Hminus the minimum value of Vdif The bus load increases as CAN nodes are added to the network,by Rdif.Consequently,Vdif decreases.The minimum value of Vaim determines the number of CAN nodes allowed on the bus.The maximum value of Vaif is specified by the upper limit during arbitration. | a The minimum value of VCANH is determined by the minimum value of VCANplus the minimum value of Vd.The maximum value of VcAN_is determined by the maximum value of VCAN_Hminus the minimum value of Vdif The bus load increases as CAN nodes are added to the network,by Rdif.Consequently,Vdif decreases.The minimum value of Vaim determines the number of CAN nodes allowed on the bus.The maximum value of Vaif is specified by the upper limit during arbitration. |

Table 3—Bus voltage parameters for low-power mode

| Parameter | Notation | Unit | min. | Value nom. | max. | Condition | |---|---|---|---|---|---|---| | Common mode bus voltage | VCANH | V | 一 | 0 | 12,0 | Measured with respect to the individual ground of each CAN node | | Common mode bus voltage | VCANL | V | -12,0 | 0 | 一 | Measured with respect to the individual ground of each CAN node | | Differential bus voltage a | Vdif | mV | -120 | 0 | 12 | Measured at each CAN node connected to the bus | | a The differential bus voltage is determined by the output behaviour ofall CAN nodes during the low-power mode.Therefore Vdif is approximately zero (see Table 8).The minimum value is determined by the requirement that a single bus driver be able to represent a dominant bit by a minimum value of Vdiff=1,2V. | a The differential bus voltage is determined by the output behaviour ofall CAN nodes during the low-power mode.Therefore Vdif is approximately zero (see Table 8).The minimum value is determined by the requirement that a single bus driver be able to represent a dominant bit by a minimum value of Vdiff=1,2V. | a The differential bus voltage is determined by the output behaviour ofall CAN nodes during the low-power mode.Therefore Vdif is approximately zero (see Table 8).The minimum value is determined by the requirement that a single bus driver be able to represent a dominant bit by a minimum value of Vdiff=1,2V. | a The differential bus voltage is determined by the output behaviour ofall CAN nodes during the low-power mode.Therefore Vdif is approximately zero (see Table 8).The minimum value is determined by the requirement that a single bus driver be able to represent a dominant bit by a minimum value of Vdiff=1,2V. | a The differential bus voltage is determined by the output behaviour ofall CAN nodes during the low-power mode.Therefore Vdif is approximately zero (see Table 8).The minimum value is determined by the requirement that a single bus driver be able to represent a dominant bit by a minimum value of Vdiff=1,2V. | a The differential bus voltage is determined by the output behaviour ofall CAN nodes during the low-power mode.Therefore Vdif is approximately zero (see Table 8).The minimum value is determined by the requirement that a single bus driver be able to represent a dominant bit by a minimum value of Vdiff=1,2V. | a The differential bus voltage is determined by the output behaviour ofall CAN nodes during the low-power mode.Therefore Vdif is approximately zero (see Table 8).The minimum value is determined by the requirement that a single bus driver be able to represent a dominant bit by a minimum value of Vdiff=1,2V. |

◎ISO 2007-All rights reserved 9 ISO 11898-5:2007(E) Table 4—Bus input current,unpowered device

| Parameter | Notation | Unit | min. | Value nom. | max. | Condition | |---|---|---|---|---|---|---| | Input leakage current | ICANH | μA | 0 | 一 | 250 a | UBus=5V,Usupply=0Vb | | Input leakage current | ICANL | μA | 0 | 一 | 250 a | UBus=5V,Usupply=0Vb | | a The maximum leakage current must stay as low as possible for devices which are intended to be used in unpowered condition, while other devices in the same network continue to communicate (see also 5.2.5).A leakage of less than 25μA is recommended forl devices which are intended to be used in unpowered condition while permanently supplied nodes might benefit from the full specified leakage range. b In case of multiple supply inputs provided by the implementation,all supply inputs shall carry o V with respect to GND. | a The maximum leakage current must stay as low as possible for devices which are intended to be used in unpowered condition, while other devices in the same network continue to communicate (see also 5.2.5).A leakage of less than 25μA is recommended forl devices which are intended to be used in unpowered condition while permanently supplied nodes might benefit from the full specified leakage range. b In case of multiple supply inputs provided by the implementation,all supply inputs shall carry o V with respect to GND. | a The maximum leakage current must stay as low as possible for devices which are intended to be used in unpowered condition, while other devices in the same network continue to communicate (see also 5.2.5).A leakage of less than 25μA is recommended forl devices which are intended to be used in unpowered condition while permanently supplied nodes might benefit from the full specified leakage range. b In case of multiple supply inputs provided by the implementation,all supply inputs shall carry o V with respect to GND. | a The maximum leakage current must stay as low as possible for devices which are intended to be used in unpowered condition, while other devices in the same network continue to communicate (see also 5.2.5).A leakage of less than 25μA is recommended forl devices which are intended to be used in unpowered condition while permanently supplied nodes might benefit from the full specified leakage range. b In case of multiple supply inputs provided by the implementation,all supply inputs shall carry o V with respect to GND. | a The maximum leakage current must stay as low as possible for devices which are intended to be used in unpowered condition, while other devices in the same network continue to communicate (see also 5.2.5).A leakage of less than 25μA is recommended forl devices which are intended to be used in unpowered condition while permanently supplied nodes might benefit from the full specified leakage range. b In case of multiple supply inputs provided by the implementation,all supply inputs shall carry o V with respect to GND. | a The maximum leakage current must stay as low as possible for devices which are intended to be used in unpowered condition, while other devices in the same network continue to communicate (see also 5.2.5).A leakage of less than 25μA is recommended forl devices which are intended to be used in unpowered condition while permanently supplied nodes might benefit from the full specified leakage range. b In case of multiple supply inputs provided by the implementation,all supply inputs shall carry o V with respect to GND. | a The maximum leakage current must stay as low as possible for devices which are intended to be used in unpowered condition, while other devices in the same network continue to communicate (see also 5.2.5).A leakage of less than 25μA is recommended forl devices which are intended to be used in unpowered condition while permanently supplied nodes might benefit from the full specified leakage range. b In case of multiple supply inputs provided by the implementation,all supply inputs shall carry o V with respect to GND. |

Table 5—Driver symmetry,normal mode

| Parameter | Notation | Unit | min. | Value nom. | max. | Condition | |---|---|---|---|---|---|---| | Driver symmetry VCAN_H+ CAN_L | VsYM | VCC | 0,9 | 1,0 | 1,1 | RL=120Ω/tol.<1%,Csplit=4,7 nF15%, fTXD=250 kHz,input impedance of oscilloscope:≤20 pF/≥1 MΩ |

Table 6—Split output voltage,optional

| Parameter | Notation | Unit | min. | Value nom. | max. | Condition | |---|---|---|---|---|---|---| | Split output voltage,normal mode loaded condition | Yspit! | VCC | 0,3 | 0,5 | 0,7 | -500 μA<Ispit<+500 μA | | Split output voltage,normal mode unloaded condition | Vspitu | VCC | 0,45 | 0,5 | 0,55 | RMeasure≥1 MQ | | Split leakage current,low-power mode | Ispit | μA | 一 | 0 | 5 | -12V<Uspit<+12V |

7.2 CAN node

7.2.1 General

The parameters given in Table 7 shall be tested at the CAN_L and CAN_H pins of each CAN node,with the CAN node disconnected from the bus.

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ISO 11898-5:2007(E) Table 7—Maximum ratings of VcAN_L,VCAN_Hand optional Vspit of CAN node

| Nominal battery voltage V | Notation | Vol V min. | tage V max. | |---|---|---|---| | 14 | VCANH | -27,0 | +40,0 | | 14 | VCANL | -27,0 | +40,0 | | 14 | Vsplit | -27,0 | +40,0 | | 28 | VCANH | -58,0 | +58,0 | | 28 | VCANL | -58,0 | +58,0 | | 28 | Vspit | -58,0 | +58,0 | | 42 | VCANH | -58,0 | +58,0 | | 42 | VCANL | -58,0 | +58,0 | | 42 | Yspit | -58,0 | +58,0 | | NOTE 1 Undisturbed operation does not have to be guaranteed. NOTE 2 There is no destruction of bus driver circuit and no time limit. | NOTE 1 Undisturbed operation does not have to be guaranteed. NOTE 2 There is no destruction of bus driver circuit and no time limit. | NOTE 1 Undisturbed operation does not have to be guaranteed. NOTE 2 There is no destruction of bus driver circuit and no time limit. | NOTE 1 Undisturbed operation does not have to be guaranteed. NOTE 2 There is no destruction of bus driver circuit and no time limit. |

The parameters given in Tables 8 to 10 shall be tested at the CAN_L and CAN_H pins of each CAN node, according to the conformance tests as specified in Clause 6 and Clause 6 of ISO 11898-2:2003. Table 8—DC parameters for recessive state of CAN node

| Parameter | Notation | Unit | min. | Value nom. | max. | Condition | |---|---|---|---|---|---|---| | Output bus voltage,normal mode | VCANH | V | 2,0 | 2,5 | 3,0 | No loada | | Output bus voltage,normal mode | VCANL | V | 2,0 | 2,5 | 3,0 | No loada | | Output bus voltage,low-power mode | VCANH | V | -0,1 | 0 | 0,1 | No load | | Output bus voltage,low-power mode | VCANL | V | -0,1 | 0 | 0,1 | No load | | Differential output bus voltage | Vdif | mV | -500 | 0 | 50 | No load | | Differential input voltage,normal modeb | VdiffN | V | -1,0 | 一 | 0,5 | c,d | | Differential input voltage,low-power moded | VdiffLP | V | -1,0 | 一 | 0,4 | c,d | | a.Due to EMC requirements,a certain matching between CAN_H and CAN_L is required(see also Table 5).Thus,the minimum value on one CAN wire cannot appear in the same time with a maximum value on the other CAN wire. b The threshold for receiving the dominant and recessive bits ensures a noise immunity of 0,3V and 0,5 V respectively.The lower value for the dominant state is motivated by the fact that a lower load resistance between CAN H and CAN_L is seen (the capacitancel of the supply voltage source is the reason that the internal resistance of the bus driver driving the dominant bit is connected in parallel to the bus load resistance). C Range for receiving a recessive bit. d Reception shall be ensured within the common mode voltage range specified in Table 1 and Table 2 respectively. | a.Due to EMC requirements,a certain matching between CAN_H and CAN_L is required(see also Table 5).Thus,the minimum value on one CAN wire cannot appear in the same time with a maximum value on the other CAN wire. b The threshold for receiving the dominant and recessive bits ensures a noise immunity of 0,3V and 0,5 V respectively.The lower value for the dominant state is motivated by the fact that a lower load resistance between CAN H and CAN_L is seen (the capacitancel of the supply voltage source is the reason that the internal resistance of the bus driver driving the dominant bit is connected in parallel to the bus load resistance). C Range for receiving a recessive bit. d Reception shall be ensured within the common mode voltage range specified in Table 1 and Table 2 respectively. | a.Due to EMC requirements,a certain matching between CAN_H and CAN_L is required(see also Table 5).Thus,the minimum value on one CAN wire cannot appear in the same time with a maximum value on the other CAN wire. b The threshold for receiving the dominant and recessive bits ensures a noise immunity of 0,3V and 0,5 V respectively.The lower value for the dominant state is motivated by the fact that a lower load resistance between CAN H and CAN_L is seen (the capacitancel of the supply voltage source is the reason that the internal resistance of the bus driver driving the dominant bit is connected in parallel to the bus load resistance). C Range for receiving a recessive bit. d Reception shall be ensured within the common mode voltage range specified in Table 1 and Table 2 respectively. | a.Due to EMC requirements,a certain matching between CAN_H and CAN_L is required(see also Table 5).Thus,the minimum value on one CAN wire cannot appear in the same time with a maximum value on the other CAN wire. b The threshold for receiving the dominant and recessive bits ensures a noise immunity of 0,3V and 0,5 V respectively.The lower value for the dominant state is motivated by the fact that a lower load resistance between CAN H and CAN_L is seen (the capacitancel of the supply voltage source is the reason that the internal resistance of the bus driver driving the dominant bit is connected in parallel to the bus load resistance). C Range for receiving a recessive bit. d Reception shall be ensured within the common mode voltage range specified in Table 1 and Table 2 respectively. | a.Due to EMC requirements,a certain matching between CAN_H and CAN_L is required(see also Table 5).Thus,the minimum value on one CAN wire cannot appear in the same time with a maximum value on the other CAN wire. b The threshold for receiving the dominant and recessive bits ensures a noise immunity of 0,3V and 0,5 V respectively.The lower value for the dominant state is motivated by the fact that a lower load resistance between CAN H and CAN_L is seen (the capacitancel of the supply voltage source is the reason that the internal resistance of the bus driver driving the dominant bit is connected in parallel to the bus load resistance). C Range for receiving a recessive bit. d Reception shall be ensured within the common mode voltage range specified in Table 1 and Table 2 respectively. | a.Due to EMC requirements,a certain matching between CAN_H and CAN_L is required(see also Table 5).Thus,the minimum value on one CAN wire cannot appear in the same time with a maximum value on the other CAN wire. b The threshold for receiving the dominant and recessive bits ensures a noise immunity of 0,3V and 0,5 V respectively.The lower value for the dominant state is motivated by the fact that a lower load resistance between CAN H and CAN_L is seen (the capacitancel of the supply voltage source is the reason that the internal resistance of the bus driver driving the dominant bit is connected in parallel to the bus load resistance). C Range for receiving a recessive bit. d Reception shall be ensured within the common mode voltage range specified in Table 1 and Table 2 respectively. | a.Due to EMC requirements,a certain matching between CAN_H and CAN_L is required(see also Table 5).Thus,the minimum value on one CAN wire cannot appear in the same time with a maximum value on the other CAN wire. b The threshold for receiving the dominant and recessive bits ensures a noise immunity of 0,3V and 0,5 V respectively.The lower value for the dominant state is motivated by the fact that a lower load resistance between CAN H and CAN_L is seen (the capacitancel of the supply voltage source is the reason that the internal resistance of the bus driver driving the dominant bit is connected in parallel to the bus load resistance). C Range for receiving a recessive bit. d Reception shall be ensured within the common mode voltage range specified in Table 1 and Table 2 respectively. |

◎ISO 2007-All rights reserved 11 Table 9—Bus input resistance of CAN node Table 10—DC parameters for dominant state of CAN node

| Parameter | Notation | Unit | min. | Value nom. | max. | Condition a | |---|---|---|---|---|---|---| | Output bus voltage,normal mode b | VCANH | V | 2,75 | 3,5 | 4,5 | Load R₁/2 | | Output bus voltage,normal mode b | VCANL | V | 0,5 | 1,5 | 2,25 | Load R₁/2 | | Differential output voltage, normal mode | Vdif | V | 1,5 | 2,0 | 3,0 | Load R{/2 | | Differential input voltage, normal mode C | Vdif | V | 0,9 | 一 | 5,0 | Load R/2 | | Differential input voltage, low-power mode | Vdif | V | 1,15 | 一 | 5,0 | Load R/2 | | a The load is connected between CAN_H and CAN_L.For a CAN node without integrated terminating resistor (normal use),this resistor is a R₁/2 resistor.For CAN nodes with an integrated terminating resistor,this is a R resistor.In this case,RL is seen between CAN_H and CAN_L instead of Rdif Due to EMC requirements a certain matching between CAN_H and CAN_L is required(see also Table 5).Thus,the minimum value on one CAN wire cannot appear in the same time with a maximum value on the other CAN wire. The threshold for receiving the dominant and recessive bits ensures a noise immunity of 0,3V and 0,5 V respectively.The lowerl value for the dominant state is motivated by the fact that a lower load resistance between CAN_H and CAN_L is seen (the capacitancel of the supply voltage source is the reason that the internal resistance of the bus driver driving the dominant bit is connected in parallel to the bus load resistance). d Range for receiving a dominant bit.Reception shall be ensured within the common mode voltage range specified in Table 1 and| Table 2 respectively. | a The load is connected between CAN_H and CAN_L.For a CAN node without integrated terminating resistor (normal use),this resistor is a R₁/2 resistor.For CAN nodes with an integrated terminating resistor,this is a R resistor.In this case,RL is seen between CAN_H and CAN_L instead of Rdif Due to EMC requirements a certain matching between CAN_H and CAN_L is required(see also Table 5).Thus,the minimum value on one CAN wire cannot appear in the same time with a maximum value on the other CAN wire. The threshold for receiving the dominant and recessive bits ensures a noise immunity of 0,3V and 0,5 V respectively.The lowerl value for the dominant state is motivated by the fact that a lower load resistance between CAN_H and CAN_L is seen (the capacitancel of the supply voltage source is the reason that the internal resistance of the bus driver driving the dominant bit is connected in parallel to the bus load resistance). d Range for receiving a dominant bit.Reception shall be ensured within the common mode voltage range specified in Table 1 and| Table 2 respectively. | a The load is connected between CAN_H and CAN_L.For a CAN node without integrated terminating resistor (normal use),this resistor is a R₁/2 resistor.For CAN nodes with an integrated terminating resistor,this is a R resistor.In this case,RL is seen between CAN_H and CAN_L instead of Rdif Due to EMC requirements a certain matching between CAN_H and CAN_L is required(see also Table 5).Thus,the minimum value on one CAN wire cannot appear in the same time with a maximum value on the other CAN wire. The threshold for receiving the dominant and recessive bits ensures a noise immunity of 0,3V and 0,5 V respectively.The lowerl value for the dominant state is motivated by the fact that a lower load resistance between CAN_H and CAN_L is seen (the capacitancel of the supply voltage source is the reason that the internal resistance of the bus driver driving the dominant bit is connected in parallel to the bus load resistance). d Range for receiving a dominant bit.Reception shall be ensured within the common mode voltage range specified in Table 1 and| Table 2 respectively. | a The load is connected between CAN_H and CAN_L.For a CAN node without integrated terminating resistor (normal use),this resistor is a R₁/2 resistor.For CAN nodes with an integrated terminating resistor,this is a R resistor.In this case,RL is seen between CAN_H and CAN_L instead of Rdif Due to EMC requirements a certain matching between CAN_H and CAN_L is required(see also Table 5).Thus,the minimum value on one CAN wire cannot appear in the same time with a maximum value on the other CAN wire. The threshold for receiving the dominant and recessive bits ensures a noise immunity of 0,3V and 0,5 V respectively.The lowerl value for the dominant state is motivated by the fact that a lower load resistance between CAN_H and CAN_L is seen (the capacitancel of the supply voltage source is the reason that the internal resistance of the bus driver driving the dominant bit is connected in parallel to the bus load resistance). d Range for receiving a dominant bit.Reception shall be ensured within the common mode voltage range specified in Table 1 and| Table 2 respectively. | a The load is connected between CAN_H and CAN_L.For a CAN node without integrated terminating resistor (normal use),this resistor is a R₁/2 resistor.For CAN nodes with an integrated terminating resistor,this is a R resistor.In this case,RL is seen between CAN_H and CAN_L instead of Rdif Due to EMC requirements a certain matching between CAN_H and CAN_L is required(see also Table 5).Thus,the minimum value on one CAN wire cannot appear in the same time with a maximum value on the other CAN wire. The threshold for receiving the dominant and recessive bits ensures a noise immunity of 0,3V and 0,5 V respectively.The lowerl value for the dominant state is motivated by the fact that a lower load resistance between CAN_H and CAN_L is seen (the capacitancel of the supply voltage source is the reason that the internal resistance of the bus driver driving the dominant bit is connected in parallel to the bus load resistance). d Range for receiving a dominant bit.Reception shall be ensured within the common mode voltage range specified in Table 1 and| Table 2 respectively. | a The load is connected between CAN_H and CAN_L.For a CAN node without integrated terminating resistor (normal use),this resistor is a R₁/2 resistor.For CAN nodes with an integrated terminating resistor,this is a R resistor.In this case,RL is seen between CAN_H and CAN_L instead of Rdif Due to EMC requirements a certain matching between CAN_H and CAN_L is required(see also Table 5).Thus,the minimum value on one CAN wire cannot appear in the same time with a maximum value on the other CAN wire. The threshold for receiving the dominant and recessive bits ensures a noise immunity of 0,3V and 0,5 V respectively.The lowerl value for the dominant state is motivated by the fact that a lower load resistance between CAN_H and CAN_L is seen (the capacitancel of the supply voltage source is the reason that the internal resistance of the bus driver driving the dominant bit is connected in parallel to the bus load resistance). d Range for receiving a dominant bit.Reception shall be ensured within the common mode voltage range specified in Table 1 and| Table 2 respectively. | a The load is connected between CAN_H and CAN_L.For a CAN node without integrated terminating resistor (normal use),this resistor is a R₁/2 resistor.For CAN nodes with an integrated terminating resistor,this is a R resistor.In this case,RL is seen between CAN_H and CAN_L instead of Rdif Due to EMC requirements a certain matching between CAN_H and CAN_L is required(see also Table 5).Thus,the minimum value on one CAN wire cannot appear in the same time with a maximum value on the other CAN wire. The threshold for receiving the dominant and recessive bits ensures a noise immunity of 0,3V and 0,5 V respectively.The lowerl value for the dominant state is motivated by the fact that a lower load resistance between CAN_H and CAN_L is seen (the capacitancel of the supply voltage source is the reason that the internal resistance of the bus driver driving the dominant bit is connected in parallel to the bus load resistance). d Range for receiving a dominant bit.Reception shall be ensured within the common mode voltage range specified in Table 1 and| Table 2 respectively. |

7.2.2 IIlustration of voltage range

Load conditions are defined in Tables 1 to 10.Figures 12 to 15 illustrate the valid voltage ranges of VCAN_H and VCAN_L ·

12 ◎ ISO 2007-All rights reserved

ISO 11898-5:2007(E) 12 11,88 11 0 Range of VCAN_H for recessive drive Range of VCANfor recessive reception V CAN_H(max)driver V CAN_H(min)driver V CAN_ -11,5 -12 Figure 12—Valid voltage range of VCAN_H for monitoring recessive bus state and for disconnected CAN node,if VCANL varies from minimum to maximum common mode range of bus ◎ISO 2007-All rights reserved 13 ISO 11898-5:2007(E) 12 11 Range ofVCAN_Hfor dominant reception Range ofVCANHfor dominant drive 0 -7 VCAN,L VCAN_H (max)driver -9 V CAN_H (min)driver -10,8 -11,1 -12 Figure 13—Valid voltage range of VCAN_H for monitoring dominant bus state and for disconnected CAN node,if VCAN_L varies from minimum to maximum common mode range of bus during normal mode

14 ◎ ISO 2007-All rights reserved

0 Figure 14—Valid voltage range of VCANHduring dominant state of CAN node which is disconnected from bus,if VCANL varies from minimum to maximum voltage level during normal mode ◎ISO 2007-All rights reserved 15 ISO 11898-5:2007(E)

| Range ofVCANHfor

dominant reception
V
CAN_L

Figure 15—Valid voltage range of VCAN_H for monitoring dominant bus state and for disconnected CAN node,if VCAN_L varies from minimum to maximum common mode range of bus during low-power mode

16 ◎ ISO 2007-All rights reserved

ISO 11898-5:2007(E)

7.2.3 AC Parameters

The parameters given in Table 11 shall be tested at the CAN_L and CAN_H pins of each CAN node,according to conformance tests 6.6 within ISO 11898-2:2003,and 6.5 and 6.6 described in this part of ISO 11898. Table 11—AC parameters of CAN node disconnected from bus

| Parameter | Notation | Unit | min. | Value nom. | max. | Condition | |---|---|---|---|---|---|---| | Bit time | B | μ | 1 | 一 | 一 | a | | Propagation delay TXD to RXDrec.to dom./dom.to rec.b | Prop | ns | 一 | 一 | 255 | Normal mode,load RL=120Ω,CL=100 pF, CRxD=15 pF,fxD=250 kHz | | Wake-up filter time,dominant bus | twake | μ | 0,5 | 一 | 5C | Low-power mode,RL=120Ω,UcM according to Table 2(min.and max.common mode bus voltage),I shall guarantee a differential dominant voltage according to Table 2 with a variable pulse length tpulse=twake(min)… wake(max) | | Internal capacitance | Cin | pF | 一 | 20 | 一 | 1 Mbit/s d | | Differential internal capacitancee | Cdiff | pF | 一 | 10 | 一 | 1 Mbit/s | | a The minimum bit time corresponds to a maximum bit rate of 1 Mbit/s.The lower end of the bit rate depends on the protocol IC or an optional permanent dominant detection circuitry preventing a permanently dominant clamped bus. b This can only be checked directly if there is access to the TXD/RXD interface.Within integrated CAN nodes,this parameter shall be measured indirectly.CL is chosen to emulate a typical transceiver loading caused by a typical bus cable and thus,is suitablefor representative propagation measurements. c It should be noted that the maximum filter time has an impact to the suitable wake-up messages,especially at high baud rates.Forl example,a 500 kBitls system,a message must carry at least three similar bit levels in a row in order to safely pass the wake-upfiter. Shorter filter time implementations might increase the risk for unwanted bus wake-ups due to noise.The specified range is a compromise between robustness against unwanted wake-ups and freedom in message selection. d Measured at CAN_Hand CAN_L referring to ground. e In adition to the internal capacitance restriction,a bus connection should also have as low an inductance as possible.This is particularly important for high bit rates.The minimum values of Cin and Cdift may be zero.The maximum tolerable values are l determined by the bit timing and the network topology parameters L,l and D(see Table 15,footnote).Proper functionality is guaranteed if occuring cable-reflected waves do not suppress the dominant differential voltage levels below Vif=0,9V and do not increase the recessive differential voltage level above Vdiff=0,5 Vat each individual CAN node(see Table 8 and 10). | a The minimum bit time corresponds to a maximum bit rate of 1 Mbit/s.The lower end of the bit rate depends on the protocol IC or an optional permanent dominant detection circuitry preventing a permanently dominant clamped bus. b This can only be checked directly if there is access to the TXD/RXD interface.Within integrated CAN nodes,this parameter shall be measured indirectly.CL is chosen to emulate a typical transceiver loading caused by a typical bus cable and thus,is suitablefor representative propagation measurements. c It should be noted that the maximum filter time has an impact to the suitable wake-up messages,especially at high baud rates.Forl example,a 500 kBitls system,a message must carry at least three similar bit levels in a row in order to safely pass the wake-upfiter. Shorter filter time implementations might increase the risk for unwanted bus wake-ups due to noise.The specified range is a compromise between robustness against unwanted wake-ups and freedom in message selection. d Measured at CAN_Hand CAN_L referring to ground. e In adition to the internal capacitance restriction,a bus connection should also have as low an inductance as possible.This is particularly important for high bit rates.The minimum values of Cin and Cdift may be zero.The maximum tolerable values are l determined by the bit timing and the network topology parameters L,l and D(see Table 15,footnote).Proper functionality is guaranteed if occuring cable-reflected waves do not suppress the dominant differential voltage levels below Vif=0,9V and do not increase the recessive differential voltage level above Vdiff=0,5 Vat each individual CAN node(see Table 8 and 10). | a The minimum bit time corresponds to a maximum bit rate of 1 Mbit/s.The lower end of the bit rate depends on the protocol IC or an optional permanent dominant detection circuitry preventing a permanently dominant clamped bus. b This can only be checked directly if there is access to the TXD/RXD interface.Within integrated CAN nodes,this parameter shall be measured indirectly.CL is chosen to emulate a typical transceiver loading caused by a typical bus cable and thus,is suitablefor representative propagation measurements. c It should be noted that the maximum filter time has an impact to the suitable wake-up messages,especially at high baud rates.Forl example,a 500 kBitls system,a message must carry at least three similar bit levels in a row in order to safely pass the wake-upfiter. Shorter filter time implementations might increase the risk for unwanted bus wake-ups due to noise.The specified range is a compromise between robustness against unwanted wake-ups and freedom in message selection. d Measured at CAN_Hand CAN_L referring to ground. e In adition to the internal capacitance restriction,a bus connection should also have as low an inductance as possible.This is particularly important for high bit rates.The minimum values of Cin and Cdift may be zero.The maximum tolerable values are l determined by the bit timing and the network topology parameters L,l and D(see Table 15,footnote).Proper functionality is guaranteed if occuring cable-reflected waves do not suppress the dominant differential voltage levels below Vif=0,9V and do not increase the recessive differential voltage level above Vdiff=0,5 Vat each individual CAN node(see Table 8 and 10). | a The minimum bit time corresponds to a maximum bit rate of 1 Mbit/s.The lower end of the bit rate depends on the protocol IC or an optional permanent dominant detection circuitry preventing a permanently dominant clamped bus. b This can only be checked directly if there is access to the TXD/RXD interface.Within integrated CAN nodes,this parameter shall be measured indirectly.CL is chosen to emulate a typical transceiver loading caused by a typical bus cable and thus,is suitablefor representative propagation measurements. c It should be noted that the maximum filter time has an impact to the suitable wake-up messages,especially at high baud rates.Forl example,a 500 kBitls system,a message must carry at least three similar bit levels in a row in order to safely pass the wake-upfiter. Shorter filter time implementations might increase the risk for unwanted bus wake-ups due to noise.The specified range is a compromise between robustness against unwanted wake-ups and freedom in message selection. d Measured at CAN_Hand CAN_L referring to ground. e In adition to the internal capacitance restriction,a bus connection should also have as low an inductance as possible.This is particularly important for high bit rates.The minimum values of Cin and Cdift may be zero.The maximum tolerable values are l determined by the bit timing and the network topology parameters L,l and D(see Table 15,footnote).Proper functionality is guaranteed if occuring cable-reflected waves do not suppress the dominant differential voltage levels below Vif=0,9V and do not increase the recessive differential voltage level above Vdiff=0,5 Vat each individual CAN node(see Table 8 and 10). | a The minimum bit time corresponds to a maximum bit rate of 1 Mbit/s.The lower end of the bit rate depends on the protocol IC or an optional permanent dominant detection circuitry preventing a permanently dominant clamped bus. b This can only be checked directly if there is access to the TXD/RXD interface.Within integrated CAN nodes,this parameter shall be measured indirectly.CL is chosen to emulate a typical transceiver loading caused by a typical bus cable and thus,is suitablefor representative propagation measurements. c It should be noted that the maximum filter time has an impact to the suitable wake-up messages,especially at high baud rates.Forl example,a 500 kBitls system,a message must carry at least three similar bit levels in a row in order to safely pass the wake-upfiter. Shorter filter time implementations might increase the risk for unwanted bus wake-ups due to noise.The specified range is a compromise between robustness against unwanted wake-ups and freedom in message selection. d Measured at CAN_Hand CAN_L referring to ground. e In adition to the internal capacitance restriction,a bus connection should also have as low an inductance as possible.This is particularly important for high bit rates.The minimum values of Cin and Cdift may be zero.The maximum tolerable values are l determined by the bit timing and the network topology parameters L,l and D(see Table 15,footnote).Proper functionality is guaranteed if occuring cable-reflected waves do not suppress the dominant differential voltage levels below Vif=0,9V and do not increase the recessive differential voltage level above Vdiff=0,5 Vat each individual CAN node(see Table 8 and 10). | a The minimum bit time corresponds to a maximum bit rate of 1 Mbit/s.The lower end of the bit rate depends on the protocol IC or an optional permanent dominant detection circuitry preventing a permanently dominant clamped bus. b This can only be checked directly if there is access to the TXD/RXD interface.Within integrated CAN nodes,this parameter shall be measured indirectly.CL is chosen to emulate a typical transceiver loading caused by a typical bus cable and thus,is suitablefor representative propagation measurements. c It should be noted that the maximum filter time has an impact to the suitable wake-up messages,especially at high baud rates.Forl example,a 500 kBitls system,a message must carry at least three similar bit levels in a row in order to safely pass the wake-upfiter. Shorter filter time implementations might increase the risk for unwanted bus wake-ups due to noise.The specified range is a compromise between robustness against unwanted wake-ups and freedom in message selection. d Measured at CAN_Hand CAN_L referring to ground. e In adition to the internal capacitance restriction,a bus connection should also have as low an inductance as possible.This is particularly important for high bit rates.The minimum values of Cin and Cdift may be zero.The maximum tolerable values are l determined by the bit timing and the network topology parameters L,l and D(see Table 15,footnote).Proper functionality is guaranteed if occuring cable-reflected waves do not suppress the dominant differential voltage levels below Vif=0,9V and do not increase the recessive differential voltage level above Vdiff=0,5 Vat each individual CAN node(see Table 8 and 10). | a The minimum bit time corresponds to a maximum bit rate of 1 Mbit/s.The lower end of the bit rate depends on the protocol IC or an optional permanent dominant detection circuitry preventing a permanently dominant clamped bus. b This can only be checked directly if there is access to the TXD/RXD interface.Within integrated CAN nodes,this parameter shall be measured indirectly.CL is chosen to emulate a typical transceiver loading caused by a typical bus cable and thus,is suitablefor representative propagation measurements. c It should be noted that the maximum filter time has an impact to the suitable wake-up messages,especially at high baud rates.Forl example,a 500 kBitls system,a message must carry at least three similar bit levels in a row in order to safely pass the wake-upfiter. Shorter filter time implementations might increase the risk for unwanted bus wake-ups due to noise.The specified range is a compromise between robustness against unwanted wake-ups and freedom in message selection. d Measured at CAN_Hand CAN_L referring to ground. e In adition to the internal capacitance restriction,a bus connection should also have as low an inductance as possible.This is particularly important for high bit rates.The minimum values of Cin and Cdift may be zero.The maximum tolerable values are l determined by the bit timing and the network topology parameters L,l and D(see Table 15,footnote).Proper functionality is guaranteed if occuring cable-reflected waves do not suppress the dominant differential voltage levels below Vif=0,9V and do not increase the recessive differential voltage level above Vdiff=0,5 Vat each individual CAN node(see Table 8 and 10). |

7.3 Medium dependent interface(MDI)specification,connector parameters

A connector used to plug CAN nodes to the bus shall meet the requirements specified in Table 12. Table 12—Connector parameters

| Parameter | Notation | Unit | min. | Value nom. | max. | |---|---|---|---|---|---| | VBAT=14V | U | V | 一 | 一 | 40 | | Voltage VBAT=28V | U | V | 一 | 一 | 58 | | VBAT=42V | U | V | 一 | 一 | 58 | | Current | I | mA | 0 | 25 | 80 | | Peak current a | Ip | mA | 一 | 一 | 500 | | Transmission frequency | f | MHz | 25 | 一 | 一 | | Transmission resistanceb | RT | mΩ | 一 | 70 | 一 | | a Time restriction:101 tB. b The differential voltage of the bus seen by the receiving CAN node depends on the line resistance between this and the transmitting CAN node.Therefore,the transmission resistance of the signal wires is limited by the bus level parameters at each CAN node. | a Time restriction:101 tB. b The differential voltage of the bus seen by the receiving CAN node depends on the line resistance between this and the transmitting CAN node.Therefore,the transmission resistance of the signal wires is limited by the bus level parameters at each CAN node. | a Time restriction:101 tB. b The differential voltage of the bus seen by the receiving CAN node depends on the line resistance between this and the transmitting CAN node.Therefore,the transmission resistance of the signal wires is limited by the bus level parameters at each CAN node. | a Time restriction:101 tB. b The differential voltage of the bus seen by the receiving CAN node depends on the line resistance between this and the transmitting CAN node.Therefore,the transmission resistance of the signal wires is limited by the bus level parameters at each CAN node. | a Time restriction:101 tB. b The differential voltage of the bus seen by the receiving CAN node depends on the line resistance between this and the transmitting CAN node.Therefore,the transmission resistance of the signal wires is limited by the bus level parameters at each CAN node. | a Time restriction:101 tB. b The differential voltage of the bus seen by the receiving CAN node depends on the line resistance between this and the transmitting CAN node.Therefore,the transmission resistance of the signal wires is limited by the bus level parameters at each CAN node. |

7.4 Physical medium specification

7.4.1 Termination resistor

The termination resistor Rused in termination A and termination B shall comply with the limits specified in Table 13. Table 13—Termination resistor

| Notation | Unit | min. | Value nom. | max. | Condition | |---|---|---|---|---|---| | | Ω | 100 | 120 | 130 | Minimum power dissipation:220 mW. | | a Dependent on the topology,the bit rate and the slew rate deviations from 120Ω may be possible.It is, however,necessary to check the applicability of other resistor values in each case.Furthermore it is possible to use a single central bus termination.In this case,the termination concentrates into one resistor with the value RL/2 offering a power dissipation of at least 440 mW.This central termination might also be implemented using a split termination consisting of two resistors with each RL/4 and at least 220 mW per resistor. The power dissipation is calculated based on the maximum differential bus voltage of 5V,which is independent from the battery supply system.In case short circuits on the bus wires towards battery have to be supported,the minimum required power dissipation increases depending on the assumed maximum short circuit bus voltage | a Dependent on the topology,the bit rate and the slew rate deviations from 120Ω may be possible.It is, however,necessary to check the applicability of other resistor values in each case.Furthermore it is possible to use a single central bus termination.In this case,the termination concentrates into one resistor with the value RL/2 offering a power dissipation of at least 440 mW.This central termination might also be implemented using a split termination consisting of two resistors with each RL/4 and at least 220 mW per resistor. The power dissipation is calculated based on the maximum differential bus voltage of 5V,which is independent from the battery supply system.In case short circuits on the bus wires towards battery have to be supported,the minimum required power dissipation increases depending on the assumed maximum short circuit bus voltage | a Dependent on the topology,the bit rate and the slew rate deviations from 120Ω may be possible.It is, however,necessary to check the applicability of other resistor values in each case.Furthermore it is possible to use a single central bus termination.In this case,the termination concentrates into one resistor with the value RL/2 offering a power dissipation of at least 440 mW.This central termination might also be implemented using a split termination consisting of two resistors with each RL/4 and at least 220 mW per resistor. The power dissipation is calculated based on the maximum differential bus voltage of 5V,which is independent from the battery supply system.In case short circuits on the bus wires towards battery have to be supported,the minimum required power dissipation increases depending on the assumed maximum short circuit bus voltage | a Dependent on the topology,the bit rate and the slew rate deviations from 120Ω may be possible.It is, however,necessary to check the applicability of other resistor values in each case.Furthermore it is possible to use a single central bus termination.In this case,the termination concentrates into one resistor with the value RL/2 offering a power dissipation of at least 440 mW.This central termination might also be implemented using a split termination consisting of two resistors with each RL/4 and at least 220 mW per resistor. The power dissipation is calculated based on the maximum differential bus voltage of 5V,which is independent from the battery supply system.In case short circuits on the bus wires towards battery have to be supported,the minimum required power dissipation increases depending on the assumed maximum short circuit bus voltage | a Dependent on the topology,the bit rate and the slew rate deviations from 120Ω may be possible.It is, however,necessary to check the applicability of other resistor values in each case.Furthermore it is possible to use a single central bus termination.In this case,the termination concentrates into one resistor with the value RL/2 offering a power dissipation of at least 440 mW.This central termination might also be implemented using a split termination consisting of two resistors with each RL/4 and at least 220 mW per resistor. The power dissipation is calculated based on the maximum differential bus voltage of 5V,which is independent from the battery supply system.In case short circuits on the bus wires towards battery have to be supported,the minimum required power dissipation increases depending on the assumed maximum short circuit bus voltage | a Dependent on the topology,the bit rate and the slew rate deviations from 120Ω may be possible.It is, however,necessary to check the applicability of other resistor values in each case.Furthermore it is possible to use a single central bus termination.In this case,the termination concentrates into one resistor with the value RL/2 offering a power dissipation of at least 440 mW.This central termination might also be implemented using a split termination consisting of two resistors with each RL/4 and at least 220 mW per resistor. The power dissipation is calculated based on the maximum differential bus voltage of 5V,which is independent from the battery supply system.In case short circuits on the bus wires towards battery have to be supported,the minimum required power dissipation increases depending on the assumed maximum short circuit bus voltage | | NOTE The lower the termination resistor value is the smaller the number of nodes in a network is due to the internal differential resistors ofall receivers connected to the bus lines CAN_H and CAN_L. | NOTE The lower the termination resistor value is the smaller the number of nodes in a network is due to the internal differential resistors ofall receivers connected to the bus lines CAN_H and CAN_L. | NOTE The lower the termination resistor value is the smaller the number of nodes in a network is due to the internal differential resistors ofall receivers connected to the bus lines CAN_H and CAN_L. | NOTE The lower the termination resistor value is the smaller the number of nodes in a network is due to the internal differential resistors ofall receivers connected to the bus lines CAN_H and CAN_L. | NOTE The lower the termination resistor value is the smaller the number of nodes in a network is due to the internal differential resistors ofall receivers connected to the bus lines CAN_H and CAN_L. | NOTE The lower the termination resistor value is the smaller the number of nodes in a network is due to the internal differential resistors ofall receivers connected to the bus lines CAN_H and CAN_L. |

Within split termination environments RL is divided into two well-matching resistors.In order to achieve good electro-magnetic emission performance,it is recommended not to exceed±1%tolerance between the two identical resistors of the split termination locally. ISO 11898-5:2007(E)

7.4.2 Optional capacitor Csplit

In case the split termination approach is used,a ceramic capacitor shall be connected between GND and the centre of the termination according to Figure 2.This capacitor is used to stabilize the centre voltage of the split termination leading to an improved EMC behaviour of the system(see Table 14). Table 14—Capacitor Cspit

| Parameter | Notation | Unit | min. | Value nom. | max. | Condition | |---|---|---|---|---|---|---| | optical capacitor | Csnita | nF | 一 | 4,7 | 一 | Minimum voltage>58V | | a The recommended range of CSplit is between 1 nF and 100 nF.It depends on network size and topology,which value achieves optimum system behaviour. | a The recommended range of CSplit is between 1 nF and 100 nF.It depends on network size and topology,which value achieves optimum system behaviour. | a The recommended range of CSplit is between 1 nF and 100 nF.It depends on network size and topology,which value achieves optimum system behaviour. | a The recommended range of CSplit is between 1 nF and 100 nF.It depends on network size and topology,which value achieves optimum system behaviour. | a The recommended range of CSplit is between 1 nF and 100 nF.It depends on network size and topology,which value achieves optimum system behaviour. | a The recommended range of CSplit is between 1 nF and 100 nF.It depends on network size and topology,which value achieves optimum system behaviour. | a The recommended range of CSplit is between 1 nF and 100 nF.It depends on network size and topology,which value achieves optimum system behaviour. |

7.4.3 Topology

The wiring topology of a CAN network should be as close as possible to a single line structure in order to avoid cable-reflected waves(see Table 15) Table 15—Network topology parameters

| Parameter | Notation | Unit | min. | Value nom. | max. | Condition | |---|---|---|---|---|---|---| | Bus length | L | m | 0 | 一 | 40 | Bit rate:1 Mbit/s a | | Cable stub length | 1 | m | 0 | 一 | 0,3 | Bit rate:1 Mbit/s a | | Node distance | D | m | 0,1 | 一 | 40 | Bit rate:1 Mbit/s a | | a At bit rates lower than 1 Mbit/s the bus length may be lengthened significantly.Depending on l,the bit rate and internal capacitances of the individual CAN nodes,other network topologies with changed lengths 1 and D may be used.In this case,the linfluence of occuring cable resonator waves on the bit representation on the bus should be carefully checked by measurements of Vaif at each CAN node(see also Table 10). | a At bit rates lower than 1 Mbit/s the bus length may be lengthened significantly.Depending on l,the bit rate and internal capacitances of the individual CAN nodes,other network topologies with changed lengths 1 and D may be used.In this case,the linfluence of occuring cable resonator waves on the bit representation on the bus should be carefully checked by measurements of Vaif at each CAN node(see also Table 10). | a At bit rates lower than 1 Mbit/s the bus length may be lengthened significantly.Depending on l,the bit rate and internal capacitances of the individual CAN nodes,other network topologies with changed lengths 1 and D may be used.In this case,the linfluence of occuring cable resonator waves on the bit representation on the bus should be carefully checked by measurements of Vaif at each CAN node(see also Table 10). | a At bit rates lower than 1 Mbit/s the bus length may be lengthened significantly.Depending on l,the bit rate and internal capacitances of the individual CAN nodes,other network topologies with changed lengths 1 and D may be used.In this case,the linfluence of occuring cable resonator waves on the bit representation on the bus should be carefully checked by measurements of Vaif at each CAN node(see also Table 10). | a At bit rates lower than 1 Mbit/s the bus length may be lengthened significantly.Depending on l,the bit rate and internal capacitances of the individual CAN nodes,other network topologies with changed lengths 1 and D may be used.In this case,the linfluence of occuring cable resonator waves on the bit representation on the bus should be carefully checked by measurements of Vaif at each CAN node(see also Table 10). | a At bit rates lower than 1 Mbit/s the bus length may be lengthened significantly.Depending on l,the bit rate and internal capacitances of the individual CAN nodes,other network topologies with changed lengths 1 and D may be used.In this case,the linfluence of occuring cable resonator waves on the bit representation on the bus should be carefully checked by measurements of Vaif at each CAN node(see also Table 10). | a At bit rates lower than 1 Mbit/s the bus length may be lengthened significantly.Depending on l,the bit rate and internal capacitances of the individual CAN nodes,other network topologies with changed lengths 1 and D may be used.In this case,the linfluence of occuring cable resonator waves on the bit representation on the bus should be carefully checked by measurements of Vaif at each CAN node(see also Table 10). |

Bibliography [1] ISO/IEC 8802-2,Information technology—Telecommunications and information exchange between systems —Local and metropolitan area networks —Specific requirements —Part 2:Logical link control

20 ◎ ISO 2007-Allrights reserved

ISO 11898-5:2007(E) ICS 43.040.15 Price based on 20 pages ◎ISO 2007-All rights reserved

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