ISO 11898-2:2024 全文(高速物理介质连接,含 CAN SIC)

标准信息:Road vehicles — Controller area network (CAN) — Part 2: High-speed medium access unit,ISO 2024 年发布(编号 90697)。CAN SIC(Signal Improvement Capability)规范本体,定义振铃抑制、回波损耗、上升/下降沿整形与 EMC 要求。 全文定位:完整正文站内查阅,章节结构与表格已保留(自动提取整理)。 📌 关键参数速查:ISO 11898-2:2024 关键参数速查

← 返回标准查阅 Road vehicles—Controller area network(CAN) 一 Part 2: High-speed physical medium attachment (PMA)sublayer Véhicules routiers—Gestionnaire de réseau de communication(CAN) 一 Partie 2:Sous-couche de I’unité d’acces au supportà haute vitesse (PMA) ISO 11898-2:2024(en) International Standard ISO 11898-2 Third edition 2024-03 ◎ ISO 2024 ISO11898-2:2024(en) COPYRIGHT PROTECTED DOCUMENT C ISO 2024 All rights reserved.Unless otherwise specified,or required in the context of its implementation,no part of this publication may be reproduced or utilized otherwise in any form or by any means,electronic or mechanical,including photocopying,or posting on the internet or an intranet,without prior written permission.Permission can be requested from either ISO at the address below or ISO’s member body in the country of the requester. ISO copyright office CP401·Ch.de Blandonnet 8 CH-1214 Vernier,Geneva Phone:+41227490111 Email:copyright@iso.org Website:www.iso.org Published in Switzerland CISO 2024-All rights reserved ISO 11898-2:2024( en) Contents Page CISO 2024-All rights reserved ISO11898-2:2024(en) Foreword ISO (the International Organization for Standardization)is a worldwide federation of national standards bodies (ISO member bodies).The work of preparing International Standards is normally carried out through ISO technical committees.Each member body interested in a subject for which a technical committee has been established has the right to be represented on that committee.International organizations, governmental and non-governmental,in liaison with ISO,also take part in the work.ISO collaborates closely with the International Electrotechnical Commission(IEC)on all matters of electrotechnical standardization. The procedures used to develop this document and those intended for its further maintenance are described in the ISO/IEC Directives,Part 1.In particular,the different approval criteria needed for the different types of ISO document should be noted.This document was drafted in accordance with the editorial rules of the ISO/IEC Directives,Part 2 (see www.iso.org/directives ). ISO draws attention to the possibility that the implementation of this document may involve the use of (a) patent(s).ISO takes no position concerning the evidence,validity or applicability of any claimed patent rights in respect thereof.As of the date of publication of this document,ISO had not received notice of (a) patent(s)which may be required to implement this document.However,implementers are cautioned that this may not represent the latest information,which may be obtained from the patent database available at www.iso.org/patents. ISO shall not be held responsible for identifying any or all such patent rights. Any trade name used in this document is information given for the convenience of users and does not constitute an endorsement. For an explanation of the voluntary nature of standards,the meaning of ISO specific terms and expressions related to conformity assessment,as well as information about ISO’s adherence to the World Trade Organization(WTO)principles in the Technical Barriersto Trade(TBT),seewww.iso.org/iso/foreword.html . This document was prepared by Technical Committee ISO/TC 22,Road vehicles,Subcommittee SC 31,Data communication. This third edition cancels and replaces the second edition(ISO 11898-2:2016),which has been technically revised. The main changes are as follows: — Clause 5 is restructured,the parameters are categorized by static parameter and dynamic parameter; 一 Table 13 with bit rates above 1 Mbit/s and up to 2 Mbit/s is in this edition Table 15 (parameter set A).Table 14 with bit rates above 2 Mbit/s and up to 5 Mbit/s is now Table 16(parameter set B).The parameter set C(see Table 17 and Table 18)in this edition is newly introduced; — AnnexA in this edition is newly introduced;it specifies HS-PMAs with the SIC mode and the FAST mode. Annex B and Annex C in this edition are Annex A and Annex B in the previous edition.The content is unchanged. A list of all parts in the ISO 11898 series can be found on the ISO website. Any feedback or questions on this document should be directed to the user’s national standards body.A complete listing of these bodies can be found at www.iso.org/members.html. CISO 2024-All rights reserved ISO11898-2:2024(en) Introduction The ISO 11898 series provides requirement specifications for the CAN data link layer and physical layer.It is intended for chip implementers,e.g.ISO 11898-1 for CAN protocol controllers and this document for CAN transceivers.Related conformance test plans are given in the ISO 16845 series.The CAN data link layerr models the open system interconnect(OSI)data link layer;it is internally subdivided into logic link control (LLC)and medium access control(MAC).ISO 11898-1 also specifies the CAN physical coding sublayer(PCS) by means of the attachment unit interface (AUI).Optionally,the PCS also provides the PWM encoding to be linked to a CAN SIC XL transceiver,which provides the PWM decoding. The open system interconnect(OSI)layers above the data link layer(e.g.the network layer)are not specified in the ISO 11898 series. Figure 1 shows the relation between the OSI layers and the CAN sublayers. OSI layers Key AUI attachment unit interface MDI medium dependent interface a Only supported by CAN XL. Figure 1—CAN data link and physical sublayers relation to the OSI model CISO 2024-All rights reserved International Standard ISO 11898-2:2024(en) Road vehicles—Controller area network(CAN) 一 Part 2: High-speed physical medium attachment(PMA)sublayer

1 Scope

This document specifies physical medium attachment (PMA)sublayers for the controller area network (CAN).This includes the high-speed(HS)PMA without and with low-power mode capability,without and with selective wake-up functionality.Additionally,this document specifies PMAs supporting the signal improvement capability (SIC)mode and the FAST mode in Annex A. The physical medium dependent(PMD) sublayer is not in the scope of this document.

2 Normative references

The following documents are referred to in the text in such a way that some orall of their content constitutes requirements of this document.For dated references,only the edition cited applies.For undated references, the latest edition of the referenced document (including any amendments)applies. ISO/IEC7498-1,Information technology—Open Systems Interconnection—Basic Reference Model:The Basic Model ISO 11898-11),Road vehicles—Controller area network (CAN)—Part 1:Data link layer and physical signalling

3 Terms and definitions

For the purposes of this document,the terms and definitions given in ISO/IEC 7498-1,ISO 11898-1 and thee following apply. ISO and IEC maintain terminology databases for use in standardization at the following addresses: 一 ISO Online browsing platform:available at https://www.iso.org/obp —IEC Electropedia:available at https://www.electropedia.org/ 3.1 active recessive intermediate high-speed physical medium attachment(HS-PMA)output drive with a dedicated lower than nominal impedance at transitions from dominant state or level_0 state towards the passive recessive (3.14) state with a dedicated duration 3.2 attachment unit interface AUI interface between the physical coding sublayer(PCS) (3.15)and the physical medium attachment(PMA)(3.16) sublayer 3.3 bus shared medium of any topology 1)Third edition under preparation.Stage at the time of publication:ISO/DIS 11898-1:2024. CISO 2024-All rights reserved ISO11898-2:2024(en) 3.4 bus state state of the medium dependent interface(MDI) (3.11), which is dominant or recessive if the physical medium attachment(PMA) (3.16) sublayer is in arbitration mode,or is level_0 or level_ 1 otherwise Note 1 to entry:The dominant state represents the logical 0 and the recessive state represents the logical 1.During simultaneous transmission of dominant and recessive bits,the resulting bus state is dominant.When no transmission is in progress,the bus(3.3)is idle.During idle time,it is in recessive state. Note 2 to entry:The level_0 state represents the logical0,and the level_ 1 state represents the logical 1. 3.5 CAN_H,CAN_L pair of ports,where VCAN_H-VCANLis positive at dominant bus state(3.4) and level_0 bus state 3.6 edge difference in bus states(3.4)between two consecutive time quanta 3.7 FAST RX mode mode in which the physical medium attachment(PMA)(3.16) sublayer drives the bus state(3.4)recessive and the receive thresholds are adjusted to distinguish between the bus states level_0 and level_ 1 3.8 FAST TX mode mode in which the physical medium attachment(PMA) (3.16) sublayer drives the bus states (3.4) level_0 and level_ 1,which are not able to overwrite each other 3.9 legacy implementation HS-PMA implementation compliant with previous ISO 11898-2 editions 3.10 low-power mode mode in which the transceiver is not capable of transmitting or receiving frames,except for the purposes of determining if a WUP or WUF is being received 3.11 MDI medium dependent interface electrical interface consisting of CAN_H and CAN_L,that defines the signal transfer between the physical medium dependent (PMD)sublayer and the physical medium attachment(PMA)(3.16)sublayer 3.12 nominal bit time duration of one bit in the arbitration phase 3.13 normal-power mode mode in which the transceiver is capable of transmitting and receiving 3.14 passive recessive final high-speed physical medium attachment(HS-PMA)output drive with nominal impedance,also known as recessive 3.15 physical coding sublayer PCS sublayer of the open system interconnect (OSI)physical layer that performs bit encoding/decoding and synchronization CISO 2024-All rights reserved ISO11898-2:2024(en) 3.16 physical medium attachment PMA sublayer of the open system interconnect (OSI)physical layer that converts physical signals into logical signals and vice versa 3.17 PWM decoding PWMD physical medium attachment(PMA)(3.16) sublayer function decoding the pulse-width modulation(PWM)bit streams into the non-return-to-zero(NRZ)bit streams 3.18 PWMencoding PWME physical coding sublayer (PCS) (3.15) function encoding the non-return-to-zero(NRZ)bit streams into thee pulse-width modulation(PWM)bit streams 3.19 receiver node that,while the bus(3.3) is not idle,is neither a transmitter(3.23)nor is it integrating 3.20 RXD port of the attachment unit interface (AUI) (3.2) used to transmit the actual state of the physical medium,in binary format,to the physical coding sublayer(PCS)(3.15) 3.21 signal improvement capability SIC capability to suppress the ringing on the MDI Note 1 to entry:It is as specified in the high-speed physical medium attachment(HS-PMA)implementation parameter set C in Table 14 and Table 17. 3.22 SIC mode mode according to the high-speed physical medium attachment(HS-PMA)during the arbitration phase Note 1 to entry:For PMA implementations,it is according to parameter set C or Annex A. 3.23 transmitter node sending CAN frames 3.24 TXD port of the attachment unit interface (AUI) (3.2) driven by the physical coding sublayer (PCS) (3.15) to control how the physical medium attachment(PMA)(3.16)influences the actual state of the physical medium

4 Abbreviated terms

For the purposes of this document,the symbols and abbreviated terms given in ISO 11898-1 and the following apply.If the definition of the term in this document is different from the definition in ISO 11898-1, this definition applies. CISO 2024-All rights reserved ISO11898-2:2024(en)

CAN	controller area network
DLC	data length code
ECU	electronic control unit
EMC	electromagnetic compatibility
ESD	electro static discharge
GND	ground
HS-PMA	high-speed PMA
NRZ	non-return-to-zero
OSI	open layer system
PMD	physical medium dependent
PN	partial networking
PWM	pulse width modulation
RF	radio frequency
WUF	wake-up frame
WUP	wake-up pattern

5 HS-PMA function

5.1 Base requirements

The HS-PMA comprises one transmitter and one receiving entity.It shall be able to bias the connected physical medium,an electric two-wire cable,relative to a common ground.The transmitter entity shall drive a differential voltage between the CAN_H and CAN_L signals to signal a logical 0〔dominant〕or shall not drive a differential voltage to signal a logical 1(recessive)to be received by other nodes connected to the very same medium.These two signals are the interface to the PMD sublayer. The HS-PMA shall provide an AUI to the physical coding sublayer as specified in ISO 11898-1.It comprises thee TXD and RXD signals as well as the GND signal.The TXD signal receives from the physical coding sublayerr the bit stream to be transmitted on the MDI.The RXD signal transmits to the physical coding sublayer thee bit stream received from the MDI. Implementations that comprise one or more HS-PMAs shall at least support the normal-power mode of operation.A low-power mode may be implemented. Some of the items specified in the following depend on the operation mode of the(part ofthe)implementation, in which the HS-PMA is included. Table 1 shows the possible combinations of HS-PMA operating modes and expected behaviour. Table 1—HS-PMA operating modes and expected behaviour

Operating mode	Bus-biasing behaviour	Bus-biasing behaviour	Bus-biasing behaviour	Transmitter behaviour
Normal-power mode	Bus	biasing	active	Dominant or recessivea
Low-power mode	Bus	biasing	active or inactive	Recessive
a Depends on input conditions as described in this document.	a Depends on input conditions as described in this document.	a Depends on input conditions as described in this document.	a Depends on input conditions as described in this document.	a Depends on input conditions as described in this document.

CISO 2024-All rights reserved ISO11898-2:2024(en) Parameters given in Clause 5 shall be fulfilled throughout the operating temperature range and supply voltage range (if not explicitly specified for unpowered)as specified individually for every HS-PMA implementation.

5.2 HS-PMA test circuit

The outputs of the HS-PMA implementation to the CAN signals are called CAN_H and CAN_L,TXD is the transmit data input and RXD is the receive data output.Figure 2 shows the external circuit used to measure the specified voltage and current parameters.RL represents the effective resistive load (bus load)for an HS-PMAimplementation,when used in a network,and C₁represents an optional split-termination capacitor. The values of Rand C₁vary for different parameters that the HS-PMA implementation needs to meet and are given as condition in the tables of related parameters. Key

1 PMA implementation

VDiff differential voltage between CAN_H and CAN_L wires VCAN_H single-ended voltage on CAN_H wire VCANL single-ended voltage on CAN_L wire CRXD capacitive load on RXD C₁ optional split-termination capacitor C₂ differential capacitive load RL differential load resistance a Power supply for the PMA implementation. Figure 2—HS-PMA test circuit

5.3 Static parameter

5.3.1 Maximum ratings of VCAN_H,VCANLand VDiff

Table 2 specifies upper and lower limit static voltages,which can be applied to CAN_H and CAN_L without causing damage,while VDiff stays within in its own maximum rating range. ◎ ISO 2024-All rights reserved ISO11898-2:2024(en) Table 2—HS-PMA maximum ratings of VCAN_H,VCAN_Land VDiff

Parameter description	Notation	Value	Value
Parameter description	Notation	Min.
[V]	Max.
[V]
Maximum rating	VDiff	-5,0	+10,0
General maximum rating	VCAN_H VCANL	-27,0	+40,0
Optional:Extended maximum rating	VCAN_H VCANL	-58,0	+58,0
a This is required regardless whether general or extended maximum rating for VCAN_H and VCANL is fulfilled.
Applies to HS-PMA implementation powered and unpowered conditions.Applies to transmit data input de-asserted and transmit data input (TXD)becomes asserted while CAN_H or/and CAN_L connected to a fixed voltage.
The maximum rating for Vpiff excludes that all combinations of VCAN_H and VCANLare compliant to this document.VDiff=VCANH-VCANL,see Figure 2.	a This is required regardless whether general or extended maximum rating for VCAN_H and VCANL is fulfilled.
Applies to HS-PMA implementation powered and unpowered conditions.Applies to transmit data input de-asserted and transmit data input (TXD)becomes asserted while CAN_H or/and CAN_L connected to a fixed voltage.
The maximum rating for Vpiff excludes that all combinations of VCAN_H and VCANLare compliant to this document.VDiff=VCANH-VCANL,see Figure 2.	a This is required regardless whether general or extended maximum rating for VCAN_H and VCANL is fulfilled.
Applies to HS-PMA implementation powered and unpowered conditions.Applies to transmit data input de-asserted and transmit data input (TXD)becomes asserted while CAN_H or/and CAN_L connected to a fixed voltage.
The maximum rating for Vpiff excludes that all combinations of VCAN_H and VCANLare compliant to this document.VDiff=VCANH-VCANL,see Figure 2.	a This is required regardless whether general or extended maximum rating for VCAN_H and VCANL is fulfilled.
Applies to HS-PMA implementation powered and unpowered conditions.Applies to transmit data input de-asserted and transmit data input (TXD)becomes asserted while CAN_H or/and CAN_L connected to a fixed voltage.
The maximum rating for Vpiff excludes that all combinations of VCAN_H and VCANLare compliant to this document.VDiff=VCANH-VCANL,see Figure 2.

5.3.2 Recessive output characteristics,bus biasing active

Table 3 specifies the recessive output characteristics when bus biasing is active. Table 3—HS-PMA recessive output characteristics,bus biasing active

Parameter	Notation	Value	Value	Value
Parameter	Notation	Min.
[V]	Nom.
[V]	Max.
[V]
Single-ended output voltage on CAN_Ha	VCANH	+2,0	+2,5	+3,0
Single-ended output voltage on CAN_Hb	VCANH rec	+2,137	+2,5	+2,887
Single-ended output voltage on CAN_L a	VCANL	+2,0	+2,5	+3,0
Single-ended output voltage on CAN_Lb	VCANLrec	+2,137	+2,5	+2,887
Differential output voltage	VDiff	-0,5	0	+0,05
NOTE The requirements in this table apply concurrently.Therefore,not all combinations of VCAN_H and VCAN_Lare compliant with the defined differential output voltage.
Measurement setup according to Figure 2(including implementations with selective wake-up function):
RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)
Measurement setup according to Figure 2:
RL=60Ω(tolerances±1%)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)	NOTE The requirements in this table apply concurrently.Therefore,not all combinations of VCAN_H and VCAN_Lare compliant with the defined differential output voltage.
Measurement setup according to Figure 2(including implementations with selective wake-up function):
RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)
Measurement setup according to Figure 2:
RL=60Ω(tolerances±1%)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)	NOTE The requirements in this table apply concurrently.Therefore,not all combinations of VCAN_H and VCAN_Lare compliant with the defined differential output voltage.
Measurement setup according to Figure 2(including implementations with selective wake-up function):
RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)
Measurement setup according to Figure 2:
RL=60Ω(tolerances±1%)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)	NOTE The requirements in this table apply concurrently.Therefore,not all combinations of VCAN_H and VCAN_Lare compliant with the defined differential output voltage.
Measurement setup according to Figure 2(including implementations with selective wake-up function):
RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)
Measurement setup according to Figure 2:
RL=60Ω(tolerances±1%)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)	NOTE The requirements in this table apply concurrently.Therefore,not all combinations of VCAN_H and VCAN_Lare compliant with the defined differential output voltage.
Measurement setup according to Figure 2(including implementations with selective wake-up function):
RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)
Measurement setup according to Figure 2:
RL=60Ω(tolerances±1%)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)

5.3.3 Recessive output characteristics,bus biasing inactive

Table 4 specifies the recessive output characteristics when bus biasing is inactive. CISO 2024-All rights reserved ISO11898-2:2024(en) Table 4—HS-PMA recessive output characteristics,bus biasing inactive

Parameter	Notation	Value a	Value a	Value a
Parameter	Notation	Min.
[V]	Nom.
[V]	Max.
[V]
Single-ended output voltage on CAN_H	VCANH	-0,1	0	+0,1
Single-ended output voltage on CAN_L	VCANL	-0,1	0	+0,1
Differential output voltage	VDiff	-0,2	0	+0,2
NOTE See 5.5.6 to determine when bias is inactive. a Measurement setup according to Figure 2:
RL>1010Ω(not present)
C₁=0pF (not present)
C2=0pF(not present)	NOTE See 5.5.6 to determine when bias is inactive. a Measurement setup according to Figure 2:
RL>1010Ω(not present)
C₁=0pF (not present)
C2=0pF(not present)	NOTE See 5.5.6 to determine when bias is inactive. a Measurement setup according to Figure 2:
RL>1010Ω(not present)
C₁=0pF (not present)
C2=0pF(not present)	NOTE See 5.5.6 to determine when bias is inactive. a Measurement setup according to Figure 2:
RL>1010Ω(not present)
C₁=0pF (not present)
C2=0pF(not present)	NOTE See 5.5.6 to determine when bias is inactive. a Measurement setup according to Figure 2:
RL>1010Ω(not present)
C₁=0pF (not present)
C2=0pF(not present)

5.3.4 Dominant output characteristics

Table 5 specifies the output characteristics during dominant state.Figure 3 illustrates the voltage range for the dominant state. Table 5—HS-PMA dominant output characteristics

Parameter	Notation	Value a	Value a	Value a	Condition b
Parameter	Notation	Min.
[V]	Nom.
[V]	Max.
[V]	Condition b
Single-ended voltage on CAN_H	VCANH	+2,75	+3,5	+4,5	RL=50Ω to 65Ω
Single-ended voltage on CANL	VCANL	+0,5	+1,5	+2,25	RL=50Ω to 65Ω
Differential voltage on normal bus load	VDiff	+1,5	+2,0	+3,0	RL=50Ω to 65Ω
Differential voltage on effective resistance during arbitration	VDiff	+1,5	Not
defined	+5,0	RL=2240Ω(See NOTE)
Optional:Differential voltage on extended bus load range	Vpiff	+1,4	+2,0	+3,3	RL=45Ωto 70Ω
NOTE Assuming a maximum R of 70Ω,this scenario covers a 32-node network(2240 Ω/70Ω=32),2240Ω is emulating a situation with up to 32 nodes transmitting dominant value simultaneously.In such case,the effective load resistance for single nodes decreases (a node does drive only a part of the nominal bus load).
l².Requirements given in this table apply concurrently.Therefore,notall combinations of VCAN_Hand VcAN_Lare compliant with the defined differential voltage (see Figure 3).
b Measurement setup according to Figure 2:
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)	NOTE Assuming a maximum R of 70Ω,this scenario covers a 32-node network(2240 Ω/70Ω=32),2240Ω is emulating a situation with up to 32 nodes transmitting dominant value simultaneously.In such case,the effective load resistance for single nodes decreases (a node does drive only a part of the nominal bus load).
l².Requirements given in this table apply concurrently.Therefore,notall combinations of VCAN_Hand VcAN_Lare compliant with the defined differential voltage (see Figure 3).
b Measurement setup according to Figure 2:
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)	NOTE Assuming a maximum R of 70Ω,this scenario covers a 32-node network(2240 Ω/70Ω=32),2240Ω is emulating a situation with up to 32 nodes transmitting dominant value simultaneously.In such case,the effective load resistance for single nodes decreases (a node does drive only a part of the nominal bus load).
l².Requirements given in this table apply concurrently.Therefore,notall combinations of VCAN_Hand VcAN_Lare compliant with the defined differential voltage (see Figure 3).
b Measurement setup according to Figure 2:
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)	NOTE Assuming a maximum R of 70Ω,this scenario covers a 32-node network(2240 Ω/70Ω=32),2240Ω is emulating a situation with up to 32 nodes transmitting dominant value simultaneously.In such case,the effective load resistance for single nodes decreases (a node does drive only a part of the nominal bus load).
l².Requirements given in this table apply concurrently.Therefore,notall combinations of VCAN_Hand VcAN_Lare compliant with the defined differential voltage (see Figure 3).
b Measurement setup according to Figure 2:
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)	NOTE Assuming a maximum R of 70Ω,this scenario covers a 32-node network(2240 Ω/70Ω=32),2240Ω is emulating a situation with up to 32 nodes transmitting dominant value simultaneously.In such case,the effective load resistance for single nodes decreases (a node does drive only a part of the nominal bus load).
l².Requirements given in this table apply concurrently.Therefore,notall combinations of VCAN_Hand VcAN_Lare compliant with the defined differential voltage (see Figure 3).
b Measurement setup according to Figure 2:
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)	NOTE Assuming a maximum R of 70Ω,this scenario covers a 32-node network(2240 Ω/70Ω=32),2240Ω is emulating a situation with up to 32 nodes transmitting dominant value simultaneously.In such case,the effective load resistance for single nodes decreases (a node does drive only a part of the nominal bus load).
l².Requirements given in this table apply concurrently.Therefore,notall combinations of VCAN_Hand VcAN_Lare compliant with the defined differential voltage (see Figure 3).
b Measurement setup according to Figure 2:
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)

CISO 2024-All rights reserved ISO11898-2:2024(en) Key Y VCAN_H and VCANL

1 range of VCAN_H(dom)

VDiff differential voltage between CAN_H and CAN_L wires VCAN_H single-ended voltage on CAN_H wire VCANL single-ended voltage on CAN_L wire Figure3—Voltage range of VCAN_H during dominant state of CAN node,when VCANLvaries from minimum to maximum voltage level(50-Ω to 65-Ω bus-load condition)

5.3.5 Maximum driver output current

Table 6 specifies the maximum HS-PMA driver output current. Table 6—Maximum HS-PMA driver output current

Parameter	Notation	Value a	Value a	Condition
Parameter	Notation	Min.
[mA]	Max.
[mA]	Condition
Absolute current on CAN_H	ICANH	not specified	115	-3V≤VCANH≤+18V
Absolute current on CAN_L	ICANL	not specified	115	-3V≤VCANL≤+18V
NOTE It is expected that the implementation does not stop driving its output dominant when the differential voltage between CAN_H and CAN_L is outside the limits given in the condition column.The minimum output current is implicitly specified in
Table 5 and thus can be expected to be above 30 mA.
a Measurement setup according to Figure 2:
RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF (not present)
CRXD=0pF(not present)	NOTE It is expected that the implementation does not stop driving its output dominant when the differential voltage between CAN_H and CAN_L is outside the limits given in the condition column.The minimum output current is implicitly specified in
Table 5 and thus can be expected to be above 30 mA.
a Measurement setup according to Figure 2:
RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF (not present)
CRXD=0pF(not present)	NOTE It is expected that the implementation does not stop driving its output dominant when the differential voltage between CAN_H and CAN_L is outside the limits given in the condition column.The minimum output current is implicitly specified in
Table 5 and thus can be expected to be above 30 mA.
a Measurement setup according to Figure 2:
RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF (not present)
CRXD=0pF(not present)	NOTE It is expected that the implementation does not stop driving its output dominant when the differential voltage between CAN_H and CAN_L is outside the limits given in the condition column.The minimum output current is implicitly specified in
Table 5 and thus can be expected to be above 30 mA.
a Measurement setup according to Figure 2:
RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF (not present)
CRXD=0pF(not present)	NOTE It is expected that the implementation does not stop driving its output dominant when the differential voltage between CAN_H and CAN_L is outside the limits given in the condition column.The minimum output current is implicitly specified in
Table 5 and thus can be expected to be above 30 mA.
a Measurement setup according to Figure 2:
RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF (not present)
CRXD=0pF(not present)

CISO 2024-All rights reserved ISO11898-2:2024(en)

5.3.6 PMA static receiver input characteristics,bus biasing active and inactive

Table 7 specifies the voltage ranges for the HS-PMA static receiver in low-power mode,when the bus biasing is active. Table 7—HS-PMA static receiver input characteristics,bus biasing active

Parameter	Notation	Value a	Value a	Condition
Parameter	Notation	Min.
[V]	Max.
[V]	Condition
Recessive state differentialinput voltage range	VDiff	-3,0	+0,5	-12,0V≤VCAN_L≤+12,0V
-12,0V≤VCANH≤+12,0V
Dominantstate differentialinput voltagerange	VDiff	+0,9	+8,0	-12,0V≤VCANL≤+12,0V
12,0V≤VCANH≤+12,0V
a Measurement setup according Figure 2: RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)
NOTE A negative differential voltage can temporarily occur when the HS-PMA is connected to a medium in which common mode chokes and/or unterminated stubs are present.The maximum positive differential voltage can temporarily occur when the HS-PMA is connected to a medium while more than one HS-PMA is sending dominant and concurrently a ground shift between the sending HS-PMAs is present.	a Measurement setup according Figure 2: RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)
NOTE A negative differential voltage can temporarily occur when the HS-PMA is connected to a medium in which common mode chokes and/or unterminated stubs are present.The maximum positive differential voltage can temporarily occur when the HS-PMA is connected to a medium while more than one HS-PMA is sending dominant and concurrently a ground shift between the sending HS-PMAs is present.	a Measurement setup according Figure 2: RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)
NOTE A negative differential voltage can temporarily occur when the HS-PMA is connected to a medium in which common mode chokes and/or unterminated stubs are present.The maximum positive differential voltage can temporarily occur when the HS-PMA is connected to a medium while more than one HS-PMA is sending dominant and concurrently a ground shift between the sending HS-PMAs is present.	a Measurement setup according Figure 2: RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)
NOTE A negative differential voltage can temporarily occur when the HS-PMA is connected to a medium in which common mode chokes and/or unterminated stubs are present.The maximum positive differential voltage can temporarily occur when the HS-PMA is connected to a medium while more than one HS-PMA is sending dominant and concurrently a ground shift between the sending HS-PMAs is present.	a Measurement setup according Figure 2: RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)
NOTE A negative differential voltage can temporarily occur when the HS-PMA is connected to a medium in which common mode chokes and/or unterminated stubs are present.The maximum positive differential voltage can temporarily occur when the HS-PMA is connected to a medium while more than one HS-PMA is sending dominant and concurrently a ground shift between the sending HS-PMAs is present.

Table 8 specifies the the voltage ranges for the HS-PMA static receiver in low-power mode,when the bus biasing is inactive. Table 8—HS-PMA static receiver input characteristics,bus biasing inactive

Parameter	Notation	Value a	Value a	Condition
Parameter	Notation	Min.
[V]	Max.
[V]	Condition
Recessive state differential input voltage range	VDiff	-3,0	+0,4	-12,0V≤VCANL≤+12,0V -12,0V≤VCANH≤+12,0V
Dominant state differential input voltage range	VDiff	+1,15	+8,0	-12,0V≤VCAN_L≤+12,0V -12,0V≤VCANH≤+12,0V
a Measurement setup according Figure2:
RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)
NOTE A negative differential voltage can temporarily occur when the HS-PMA is connected to a medium in which common mode chokes and/or unterminated stubs are present.The maximum positive diferential voltage can temporarily occur when the HS-PMA is connected to a medium while more than one HS-PMA is sending dominant and concurrently a ground shift between the sending HS-PMAs is present.	a Measurement setup according Figure2:
RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)
NOTE A negative differential voltage can temporarily occur when the HS-PMA is connected to a medium in which common mode chokes and/or unterminated stubs are present.The maximum positive diferential voltage can temporarily occur when the HS-PMA is connected to a medium while more than one HS-PMA is sending dominant and concurrently a ground shift between the sending HS-PMAs is present.	a Measurement setup according Figure2:
RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)
NOTE A negative differential voltage can temporarily occur when the HS-PMA is connected to a medium in which common mode chokes and/or unterminated stubs are present.The maximum positive diferential voltage can temporarily occur when the HS-PMA is connected to a medium while more than one HS-PMA is sending dominant and concurrently a ground shift between the sending HS-PMAs is present.	a Measurement setup according Figure2:
RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)
NOTE A negative differential voltage can temporarily occur when the HS-PMA is connected to a medium in which common mode chokes and/or unterminated stubs are present.The maximum positive diferential voltage can temporarily occur when the HS-PMA is connected to a medium while more than one HS-PMA is sending dominant and concurrently a ground shift between the sending HS-PMAs is present.	a Measurement setup according Figure2:
RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)
NOTE A negative differential voltage can temporarily occur when the HS-PMA is connected to a medium in which common mode chokes and/or unterminated stubs are present.The maximum positive diferential voltage can temporarily occur when the HS-PMA is connected to a medium while more than one HS-PMA is sending dominant and concurrently a ground shift between the sending HS-PMAs is present.

5.3.7 Receiver input resistance

Figure 4 shows an equivalent circuitry of the HS-PMA internal differential input resistance.Table 9specifies the HS-PMA receiver input resistance parameter. Table 10 specifies the HS-PMA receiver input resistance matching parameters. CISO 2024-All rights reserved ISO11898-2:2024(en) RsE_SIC_pas_rec RsE_SIC_pas_rec CAN_L 二二二 Vbus_Bias Figure 4—Illustration of HS-PMA internal differential input resistance Table 9—HS-PMA receiver input resistance

Parameter	Parameter	Parameter	Notation	Value	Value	Condition
Parameter	Parameter	Parameter	Notation	Min.
[kΩ2]	Max.
[kΩ]	Condition
Differential	internal	resistance	RDIFFpas reca	12	100	-2V≤VCAN_L VCAN_H≤+7V
Single-ended	internal	resistance	RSE_pas_recH RsE pas recL	6	50	-2V≤VCAN_L VCAN_H≤+7V
a RDIFEpas rec=RsE_pas recH+RsEpas recL	a RDIFEpas rec=RsE_pas recH+RsEpas recL	a RDIFEpas rec=RsE_pas recH+RsEpas recL	a RDIFEpas rec=RsE_pas recH+RsEpas recL	a RDIFEpas rec=RsE_pas recH+RsEpas recL	a RDIFEpas rec=RsE_pas recH+RsEpas recL	a RDIFEpas rec=RsE_pas recH+RsEpas recL

Table 10—HS-PMA receiver input resistance matching

Parameter	Notation	Value	Value	Condition
Parameter	Notation	Min.	Max.	Condition
Matchinga of internal resistance	mR	-0,03	+0,03	VCANL,VCAN_H:
+5V
a The matching shall be calculated as mR=2×(RsEH-RsELJ/(RsEH+RsEL).	a The matching shall be calculated as mR=2×(RsEH-RsELJ/(RsEH+RsEL).	a The matching shall be calculated as mR=2×(RsEH-RsELJ/(RsEH+RsEL).	a The matching shall be calculated as mR=2×(RsEH-RsELJ/(RsEH+RsEL).	a The matching shall be calculated as mR=2×(RsEH-RsELJ/(RsEH+RsEL).

5.3.8 Maximum leakage currents of CAN_H and CAN_L

An unpowered HS-PMA implementation shall not disturb the communication of other HS-PMAs that are connected to the same medium. Table 11 specifies the HS-PMA maximum leakage currents. Table 11—HS-PMA maximum leakage currents on CAN_H and CAN_L,unpowered

Parameter	Notation	Value	Value
Parameter	Notation	Min.
[μA]	Max.
[μA]
Leakage current on CAN_H,CAN_L	ICAN_H IcANL	-10	+10
VCANH=5V,VCANL=5V,all supply inputs are connected to GND. Positive currents are flowing into the implementation.	VCANH=5V,VCANL=5V,all supply inputs are connected to GND. Positive currents are flowing into the implementation.	VCANH=5V,VCANL=5V,all supply inputs are connected to GND. Positive currents are flowing into the implementation.	VCANH=5V,VCANL=5V,all supply inputs are connected to GND. Positive currents are flowing into the implementation.

◎ ISO 2024-All rights reserved ISO11898-2:2024(en)

5.4 Dynamic

5.4.1 Driver

parameter symmetry In order to achieve a level of RFemission that is acceptably low,the transmitter shall meet the driver signal symmetry as specified in Table 12. Table 12—HS-PMA driver symmetry

Parameter	Notation	Value C	Value C	Value C
Parameter	Notation	Min.	Nom.	Max.
Driver symmetry based on Vcca	Vsym vcc	+0,9	+1,0	+1,1
Driver symmetry based on Vrec sumb	Vsym vrec	+0,9	+1,0	+1,1
aVsym_vcc=(VCAN_H+VCAN_LJ/Vcc,with Vcc being the power supply of the transmitter
bVsym_vrec=(VCAN_H+VCAN_LJ/Vsum,without Vcc reference Vrec_sum=VCAN_H_rec+VCANL_rec
Ysym_vec and Vsym_vrec shall be observed during dominant state and recessive state and also during the transition from dominant to recessive and vice versa,while TXD is stimulated by a square wave signal with a frequency that corresponds to the highest bit rate for which the HS-PMA implementation is intended,however,at most 1 MHz (2 Mbit/s)(HS-PMA in normal-power mode).
C Measurement setup according to Figure 2:
RL=60Ω(tolerance≤±1%)
C₁=4,7nF(tolerance≤±5%)
C₂=0 pF(not present)
CRxD=0 pF(not present)	aVsym_vcc=(VCAN_H+VCAN_LJ/Vcc,with Vcc being the power supply of the transmitter
bVsym_vrec=(VCAN_H+VCAN_LJ/Vsum,without Vcc reference Vrec_sum=VCAN_H_rec+VCANL_rec
Ysym_vec and Vsym_vrec shall be observed during dominant state and recessive state and also during the transition from dominant to recessive and vice versa,while TXD is stimulated by a square wave signal with a frequency that corresponds to the highest bit rate for which the HS-PMA implementation is intended,however,at most 1 MHz (2 Mbit/s)(HS-PMA in normal-power mode).
C Measurement setup according to Figure 2:
RL=60Ω(tolerance≤±1%)
C₁=4,7nF(tolerance≤±5%)
C₂=0 pF(not present)
CRxD=0 pF(not present)	aVsym_vcc=(VCAN_H+VCAN_LJ/Vcc,with Vcc being the power supply of the transmitter
bVsym_vrec=(VCAN_H+VCAN_LJ/Vsum,without Vcc reference Vrec_sum=VCAN_H_rec+VCANL_rec
Ysym_vec and Vsym_vrec shall be observed during dominant state and recessive state and also during the transition from dominant to recessive and vice versa,while TXD is stimulated by a square wave signal with a frequency that corresponds to the highest bit rate for which the HS-PMA implementation is intended,however,at most 1 MHz (2 Mbit/s)(HS-PMA in normal-power mode).
C Measurement setup according to Figure 2:
RL=60Ω(tolerance≤±1%)
C₁=4,7nF(tolerance≤±5%)
C₂=0 pF(not present)
CRxD=0 pF(not present)	aVsym_vcc=(VCAN_H+VCAN_LJ/Vcc,with Vcc being the power supply of the transmitter
bVsym_vrec=(VCAN_H+VCAN_LJ/Vsum,without Vcc reference Vrec_sum=VCAN_H_rec+VCANL_rec
Ysym_vec and Vsym_vrec shall be observed during dominant state and recessive state and also during the transition from dominant to recessive and vice versa,while TXD is stimulated by a square wave signal with a frequency that corresponds to the highest bit rate for which the HS-PMA implementation is intended,however,at most 1 MHz (2 Mbit/s)(HS-PMA in normal-power mode).
C Measurement setup according to Figure 2:
RL=60Ω(tolerance≤±1%)
C₁=4,7nF(tolerance≤±5%)
C₂=0 pF(not present)
CRxD=0 pF(not present)	aVsym_vcc=(VCAN_H+VCAN_LJ/Vcc,with Vcc being the power supply of the transmitter
bVsym_vrec=(VCAN_H+VCAN_LJ/Vsum,without Vcc reference Vrec_sum=VCAN_H_rec+VCANL_rec
Ysym_vec and Vsym_vrec shall be observed during dominant state and recessive state and also during the transition from dominant to recessive and vice versa,while TXD is stimulated by a square wave signal with a frequency that corresponds to the highest bit rate for which the HS-PMA implementation is intended,however,at most 1 MHz (2 Mbit/s)(HS-PMA in normal-power mode).
C Measurement setup according to Figure 2:
RL=60Ω(tolerance≤±1%)
C₁=4,7nF(tolerance≤±5%)
C₂=0 pF(not present)
CRxD=0 pF(not present)

5.4.2 Optional transmit dominant timeout

An implementation of an HS-PMA may limit the duration of dominant transmission in order not to prevent other CAN nodes from communication when the TXD input is permanently asserted.The HS-PMA implementation should implement atimeout.Table 13 recommends the optional HS-PMA transmit dominant timeout value range. Table 13—Optional HS-PMA transmit dominant timeout

Parameter	Notation	Value a	Value a
Parameter	Notation	Min.
[ms]	Max.
[ms]
Transmit dominant timeouta	tdom	0,8	10,0
a Aminimum value of 0,3 ms is accepted for legacy implementations.	a Aminimum value of 0,3 ms is accepted for legacy implementations.	a Aminimum value of 0,3 ms is accepted for legacy implementations.	a Aminimum value of 0,3 ms is accepted for legacy implementations.

NOTE There is a relation between the tdom minimum value and the minimum bit rate.A tdom minimum value of 0,8ms accommodates 17 consecutive dominant bits at bit rates greater than or equalto 21,6kbit/s and 36 consecutive dominant bits at bit rates greater than or equal to 45,8 kbit/s.The value 17 reflects PMA implementation attempts to send a dominant bit and every time sees a recessive level at the receive data input.The value 36 reflects six consecutive error frames when there is a bit error in the last bit of the first five attempts.

5.4.3 Transmitter and receiver timing behaviour

Figure 5 defines the HS-PMA implementation timing. Table 14 specifies the the HS-PMA implementation loop-delay requirements for parameter set A,parameter set B,and parameter set C. Table 15 specifies the HS-PMA implementation data signal timing requirements for parameter set A. Table 16 specifies the HS- PMA implementation data signal timing requirements for parameter set B. Table 17 and Table 18 specify HS-PMA implementation data signal timing requirements for parameter set C. NOTE HS-PMA implementations with signal improvement capability developed prior to this document can refer to the CiA 601-4 specification. CISO 2024-All rights reserved ISO11898-2:2024(en) Key Bit(TXD)nominal bit time of the bit rates the HS-PMA supports Figure 5—HS-PMA implementation timing definitions Ta ble 14—HS-PMA implementation loop-delay requirement for parameter sets A,Band C

Parameter	Notation	Value b	Value b
Parameter	Notation	Min.
[ns]	Max.
[ns]
Loop delay for parameter set A and parameter set Ba	tLoop	not specified	255
Loop delay for parameter set Ca	tLoop	not specified	190
Propagation delay from TXD to CAN_H/CAN_L for parameter set C	tprop(TXD_BUS)	not specified	80
Propogation delay from CAN_H/CAN_Lto RXD for parameter set C	tprop(BUS_RXD)	not specified	110
a Time span from signaledge on TXD input to the next signal edge with the same polarity on RXD output,the maximum of delay of both signal edges is to be considered.
bMeasurement setup according to Figure 2:
RL=60Ω(tolerance≤±1%)
C₁=0pF(not present)
C₂=100 pF(tolerance≤±1%)
CRxD=15pF(tolerance≤±1%)
Measurement according to Figure 5:
The input signal on TXD shall have rise and fall times (10 %/90 %)of less than 10 ns.	a Time span from signaledge on TXD input to the next signal edge with the same polarity on RXD output,the maximum of delay of both signal edges is to be considered.
bMeasurement setup according to Figure 2:
RL=60Ω(tolerance≤±1%)
C₁=0pF(not present)
C₂=100 pF(tolerance≤±1%)
CRxD=15pF(tolerance≤±1%)
Measurement according to Figure 5:
The input signal on TXD shall have rise and fall times (10 %/90 %)of less than 10 ns.	a Time span from signaledge on TXD input to the next signal edge with the same polarity on RXD output,the maximum of delay of both signal edges is to be considered.
bMeasurement setup according to Figure 2:
RL=60Ω(tolerance≤±1%)
C₁=0pF(not present)
C₂=100 pF(tolerance≤±1%)
CRxD=15pF(tolerance≤±1%)
Measurement according to Figure 5:
The input signal on TXD shall have rise and fall times (10 %/90 %)of less than 10 ns.	a Time span from signaledge on TXD input to the next signal edge with the same polarity on RXD output,the maximum of delay of both signal edges is to be considered.
bMeasurement setup according to Figure 2:
RL=60Ω(tolerance≤±1%)
C₁=0pF(not present)
C₂=100 pF(tolerance≤±1%)
CRxD=15pF(tolerance≤±1%)
Measurement according to Figure 5:
The input signal on TXD shall have rise and fall times (10 %/90 %)of less than 10 ns.

CISO 2024-All rights reserved ISO11898-2:2024(en) Table 15—HS-PMA implementation data signal timing requirements for parameter set A Value d Parameter Transmitted recessive bit width variation Received recessive bit width variation Receiver timing symmetry a t△Bit(Bus)=Bit(Bus)-Bit(TXD) t△Bit(RXD)=tBi(RXD)-Bit(TXD) Ct△Rec=tBit(RXD)-tBit(Bus) The requirements in this table apply concurrently.Therefore,not all combinations of t△Bit(Bus)and tARec are compliant witht△Bit(RXD) · d Measurement setup according to 2: RL=60Ω(tolerances±1%) C₁=0pF(not present) C₂=100 pF(tolerance≤±1%) CRxD=15 pF(tolerance≤±1%) Measurement according to Figure 5: The input signal on TXD shall have rise and fall times (10 %/90 %)of less than 10 ns. Table 16—HS-PMA implementation data signal timing requirements for parameter set B

Parameter	Notation	Valued	Valued
Parameter	Notation	Min.
[ns]	Max.
[ns]
Transmitted recessive bit width variation	t△Bit(Bus)	-45	+10
Received recessive bit width variation	t△Bit(RXD)	-80	+20
Receiver timing symmetry variation	t△RecC	-45	+15
a t△Bit(Bus)=tBit(Bus)-tBit(TXD)
t△Bit(RXD)=tBit(RXD)-Bit(TXD)
tARec=Bit(RXD)-Bit(Bus)
The requirements in this table apply concurrently.Therefore,not all combinations of t△Bit(Bus)and t△Rec are compliant witht△Bit(RXD) ·
d Measurement setup according to Figure2:
RL=60Ω(tolerance≤±1%)
C₁=0 pF(not present)
C₂=100 pF(tolerance≤±1%)
CRxD=15pF(tolerance≤±1%)
Measurement according to Figure 5:
The input signal on TXD shall have rise and fall times(10 %/90 %)of less than 10 ns.
NOTE Limits for tit(Bus andtBit(RXD are not defined for intended use with bit rates upto 1 Mbit/s.	a t△Bit(Bus)=tBit(Bus)-tBit(TXD)
t△Bit(RXD)=tBit(RXD)-Bit(TXD)
tARec=Bit(RXD)-Bit(Bus)
The requirements in this table apply concurrently.Therefore,not all combinations of t△Bit(Bus)and t△Rec are compliant witht△Bit(RXD) ·
d Measurement setup according to Figure2:
RL=60Ω(tolerance≤±1%)
C₁=0 pF(not present)
C₂=100 pF(tolerance≤±1%)
CRxD=15pF(tolerance≤±1%)
Measurement according to Figure 5:
The input signal on TXD shall have rise and fall times(10 %/90 %)of less than 10 ns.
NOTE Limits for tit(Bus andtBit(RXD are not defined for intended use with bit rates upto 1 Mbit/s.	a t△Bit(Bus)=tBit(Bus)-tBit(TXD)
t△Bit(RXD)=tBit(RXD)-Bit(TXD)
tARec=Bit(RXD)-Bit(Bus)
The requirements in this table apply concurrently.Therefore,not all combinations of t△Bit(Bus)and t△Rec are compliant witht△Bit(RXD) ·
d Measurement setup according to Figure2:
RL=60Ω(tolerance≤±1%)
C₁=0 pF(not present)
C₂=100 pF(tolerance≤±1%)
CRxD=15pF(tolerance≤±1%)
Measurement according to Figure 5:
The input signal on TXD shall have rise and fall times(10 %/90 %)of less than 10 ns.
NOTE Limits for tit(Bus andtBit(RXD are not defined for intended use with bit rates upto 1 Mbit/s.	a t△Bit(Bus)=tBit(Bus)-tBit(TXD)
t△Bit(RXD)=tBit(RXD)-Bit(TXD)
tARec=Bit(RXD)-Bit(Bus)
The requirements in this table apply concurrently.Therefore,not all combinations of t△Bit(Bus)and t△Rec are compliant witht△Bit(RXD) ·
d Measurement setup according to Figure2:
RL=60Ω(tolerance≤±1%)
C₁=0 pF(not present)
C₂=100 pF(tolerance≤±1%)
CRxD=15pF(tolerance≤±1%)
Measurement according to Figure 5:
The input signal on TXD shall have rise and fall times(10 %/90 %)of less than 10 ns.
NOTE Limits for tit(Bus andtBit(RXD are not defined for intended use with bit rates upto 1 Mbit/s.

CISO 2024-All rights reserved ISO11898-2:2024(en) Table 17—HS-PMA implementation data signal timing requirements for parameter set C

Parameterr	Notation	Value d	Value d
Parameterr	Notation	Min.
[ns]	Max.
[ns]
Transmitted recessive bit width variation	t△Bit(Bus)	-10	+10
Received recessive bit width variation	L△Bit(RXD)	-30	+20
Receiver timing symmetry variation	t△RecC	-20	+15
a △Bit(Bus)=tBit(Bus)-Bit(TXD)
△Bit(RXD)=Bit(RXD)-Bit(TXD)
C t△Rec=tBit(RXD)-tBit(Bus)
All requirements in this table apply concurrently.Therefore,not all combinations of t△Bit(Bus)and t△Rec are compliant witht△Bit(RXD) ·
a Measurement setup according to Figure2:
RL=60Ω(tolerance≤±1%)
C₁=0pF(not present)
C₂=100 pF(tolerance≤±1%)
CRxD=15pF (tolerance≤±1%)	a △Bit(Bus)=tBit(Bus)-Bit(TXD)
△Bit(RXD)=Bit(RXD)-Bit(TXD)
C t△Rec=tBit(RXD)-tBit(Bus)
All requirements in this table apply concurrently.Therefore,not all combinations of t△Bit(Bus)and t△Rec are compliant witht△Bit(RXD) ·
a Measurement setup according to Figure2:
RL=60Ω(tolerance≤±1%)
C₁=0pF(not present)
C₂=100 pF(tolerance≤±1%)
CRxD=15pF (tolerance≤±1%)	a △Bit(Bus)=tBit(Bus)-Bit(TXD)
△Bit(RXD)=Bit(RXD)-Bit(TXD)
C t△Rec=tBit(RXD)-tBit(Bus)
All requirements in this table apply concurrently.Therefore,not all combinations of t△Bit(Bus)and t△Rec are compliant witht△Bit(RXD) ·
a Measurement setup according to Figure2:
RL=60Ω(tolerance≤±1%)
C₁=0pF(not present)
C₂=100 pF(tolerance≤±1%)
CRxD=15pF (tolerance≤±1%)	a △Bit(Bus)=tBit(Bus)-Bit(TXD)
△Bit(RXD)=Bit(RXD)-Bit(TXD)
C t△Rec=tBit(RXD)-tBit(Bus)
All requirements in this table apply concurrently.Therefore,not all combinations of t△Bit(Bus)and t△Rec are compliant witht△Bit(RXD) ·
a Measurement setup according to Figure2:
RL=60Ω(tolerance≤±1%)
C₁=0pF(not present)
C₂=100 pF(tolerance≤±1%)
CRxD=15pF (tolerance≤±1%)

Table 18 specifies the HS-PMA implementation SIC timing and impedance for parameter set C. Table 18—HS-PMA implementation SIC timing and impedance for parameter set C

Parameter	Notation	Value	Value	Condition
Parameter	Notation	Min.	Max.	Condition
Differential internal resistance (CAN_H to CAN_L)	RDIFE_act_rec	75Ω	133Ω	+2V≤VCAN_H/L≤Vcc-2V,if
Rse fulfils RsE_act_rec otherwise -12V≤VCAN_H/L≤+12V
Optional internal single-ended resist- ance	RsE_SIC_actrec	37,5Ω	66,5Ω	+2V≤VCANH/L≤Vcc-2V,if Rse fulfils
RsE_sic otherwise -12V≤VCAN_H/L≤Vcc +12V
Starttime of active signal improve- ment phase	tact_rec_start	n.a.	120ns	Measured from rising TXD edge with<5ns slope at 50%threshold
End time of active signal improve- ment phase	tact_recend	355ns	n.a.	Measured from rising TXD edge with<5ns slope at 50%threshold
Start time of passive recessive phase	tpas_rec_start	n.a.	530 ns	Measured from rising TXD edge
with<5ns slope at 50 %threshold with
RDIFF≥min.RDIF REC and RsE≥min.Rse.a
a Formerly specified in ISO11898-2:2016,Table 10.	a Formerly specified in ISO11898-2:2016,Table 10.	a Formerly specified in ISO11898-2:2016,Table 10.	a Formerly specified in ISO11898-2:2016,Table 10.	a Formerly specified in ISO11898-2:2016,Table 10.

Figure 6 defines the SIC timing. CISO 2024-All rights reserved ISO11898-2:2024(en) Figure 6—SIC timing definitions

5.5 Wake-up from low-power mode

5.5.1 Wake-up procedures

When an implementation comprising one or more HS-PMAs implements a low-power mode,the HS-PMA can signal a wake-up event.Table 19 lists the wake-up procedures for defined types of HS-PMA implementations. Table 19—HS-PMA wake-up implementations

Type of HS-PMA implementation	Required wake-up mechanism
Without low-power mode	No wake-up
With low-power mode,but without selective wake- up	Either basic wake-up or wake-up pat- tern (WUP)wake-up
With selective wake-up	Selective wake-up frame (WUF)and wake-up pattern(WUP)wake-up

5.5.2 General requirement

In case more than one wake-up procedure is implemented in an HS-PMA,the wake-up procedure to be used shall be configurable.

5.5.3 Basic wake-up

After having received a dominant state for the duration of at least tFilter,the HS-PMA shall detect a wake-up.

5.5.4 Via wake-up pattern

Upon receiving two consecutive dominant states each for duration of at least tFilter separated by a recessive state with a duration of at least tFilter a wake-up event shall happen.This method is illustrated inFigure 7. ◎ ISO 2024-All rights reserved ISO11898-2:2024(en) Key

1 INI state

2 state A

3 state B

4 state C:wake-up detected,entering this state shall signal the bus wake-up event

5 wait state

Figure 7—Wake-up finite state machine The finite state machine in Figure 7 specifies the wake-up behaviour for all operation modes.When entering state A the optional timer,twake,shall be reset and when entering the Wait state the tFilter timer shall bee reset. Table 20 specifies the wake-up control timings and Figure 8 defines the wake-up reaction time. CISO 2024-All rights reserved ISO11898-2:2024(en) Table 20—PMA voltage wake-up control timings

Parameter	Notation	Value	Value	Condition
Parameter	Notation	Min.
[μs]	Max.
[μs]	Condition
CAN activity filter time,longa	Filter	0,5	5,0	Bus voltages shall be as specified in
Table 8.
CAN activity filter time,shortb	tFilter	0,15	1,8	Bus voltages shall be as specified in
Table A.2.
Wake-up timeout	twake	800,0	10000,0	Optional timer
Wake-up pattern signalling	tFlag	not defined	250,0	Measured from the completed wake- up pattern,see Figure 8
a Implementations do not need to meet this timing,in case the”CAN activity filter time,short”is met.It should be noted that the maximum filter time has an impact to the suitable wake-up pattern,especially at high bit rates.For example,in a 500-kbit/s network,a wake-up pattern shall carry at least three similar bit levels in a row in order to safely pass the wake-up filter.Shorterl [filter time implementations can increase the risk for unwanted bus wake-ups due to noise.The specified range is a compromise between robustness against unwanted wake-ups and freedom in frame selection.
bImplementations do not need to meet this timing,in case the“CAN activity filter time,long”is met.	a Implementations do not need to meet this timing,in case the”CAN activity filter time,short”is met.It should be noted that the maximum filter time has an impact to the suitable wake-up pattern,especially at high bit rates.For example,in a 500-kbit/s network,a wake-up pattern shall carry at least three similar bit levels in a row in order to safely pass the wake-up filter.Shorterl [filter time implementations can increase the risk for unwanted bus wake-ups due to noise.The specified range is a compromise between robustness against unwanted wake-ups and freedom in frame selection.
bImplementations do not need to meet this timing,in case the“CAN activity filter time,long”is met.	a Implementations do not need to meet this timing,in case the”CAN activity filter time,short”is met.It should be noted that the maximum filter time has an impact to the suitable wake-up pattern,especially at high bit rates.For example,in a 500-kbit/s network,a wake-up pattern shall carry at least three similar bit levels in a row in order to safely pass the wake-up filter.Shorterl [filter time implementations can increase the risk for unwanted bus wake-ups due to noise.The specified range is a compromise between robustness against unwanted wake-ups and freedom in frame selection.
bImplementations do not need to meet this timing,in case the“CAN activity filter time,long”is met.	a Implementations do not need to meet this timing,in case the”CAN activity filter time,short”is met.It should be noted that the maximum filter time has an impact to the suitable wake-up pattern,especially at high bit rates.For example,in a 500-kbit/s network,a wake-up pattern shall carry at least three similar bit levels in a row in order to safely pass the wake-up filter.Shorterl [filter time implementations can increase the risk for unwanted bus wake-ups due to noise.The specified range is a compromise between robustness against unwanted wake-ups and freedom in frame selection.
bImplementations do not need to meet this timing,in case the“CAN activity filter time,long”is met.	a Implementations do not need to meet this timing,in case the”CAN activity filter time,short”is met.It should be noted that the maximum filter time has an impact to the suitable wake-up pattern,especially at high bit rates.For example,in a 500-kbit/s network,a wake-up pattern shall carry at least three similar bit levels in a row in order to safely pass the wake-up filter.Shorterl [filter time implementations can increase the risk for unwanted bus wake-ups due to noise.The specified range is a compromise between robustness against unwanted wake-ups and freedom in frame selection.
bImplementations do not need to meet this timing,in case the“CAN activity filter time,long”is met.

1	2	3	7	8
6	6	6	7	8

a)Correct wake-up pattern with PMA low-power mode

1	2	5	1
6	6	6	6

b)Incorrect wake-up pattern,dominant phase longer than twake CISO 2024-All rights reserved ISO11898-2:2024(en) c)Incorrect wake-up pattern,recessive phase longer than twake Key

1 INI state

2 in state A

3 in state B

4 in state C

5 in Wait state

6 in low-power mode

7 wake-up detected

8 wake-up flagged

Figure 8—Wake-up reaction time,a)to c)

5.5.5 Selective wake-up

5.5.5.1 General

Upon detection of a wake-up frame (WUF),a wake-up event shall happen.Decoding of CAN frames in either classical base frame format (CBFF)or classical extended frame format (CEFF)and acceptance as a WUF is done by the HS-PMA.If enabled,decoding of CAN frames shall be possible in normal-power mode and low- power mode.The acceptance procedure is described in detail in the following subclauses. After the bias reaction time,tBias,has elapsed,the implementation may ignore up to four (or up to eight when bit rate higher than 500 kbit/s)frames in CBFF and CEFF and shall not ignore any following frame in CBFF and CEFF. In case of erroneous communication,the HS-PMA shall signal a wake-up upon or after an overflow of thee internal error counter.

5.5.5.2 Behaviour during transitions between normal-power mode to low-power mode

If selective wake-up is enabled prior to the mode change and the HS-PMA is not anymore ignoring frames, decoding of CAN data frames and CAN remote frames shall also be supported during mode transitions, which have the frame detection functionality enabled.If the received frame is a valid WUF,the transceiverr shall indicate a wake-up.If enabled,decoding of CAN data shall be possible in normal-power mode and low- power mode. CISO 2024-All rights reserved ISO11898-2:2024(en)

5.5.5.3 Bit decoding

A received classical CAN frame shall be decoded correctly when the timing of the differential voltage between CAN_H and CAN_L complies with one of the two following types of signals: —the bit stream consists of multiple instances of the signal shape A(to handle ringing); 一 the bit stream can be assembled out of multiple instances of the signal shape B1 and one instance of signal shape B2(to handle sender clock tolerance and loss of arbitration). These two types of signals are specified in Figure 9. Key

1 recessive

2 dominant

n₁ number of consecutive dominant bits{1,2,3,4,5} n₂ number of bits between two falling edges {2,3,…,10};n₂>n₁ tA 0≤tA≤55%of tBit(implementation-specific higher maximum values fortAare allowed) tB 0≤tB≤5%oftBit(implementation-specific higher maximum values fortB are allowed) tBit nominal bit time dfs transceivers according to this document shalltolerate sender clock frequency deviations up to at least 0,5 % NOTE Often used values for tBit are 2μs,4μs and 8μs. Figure 9—Signal shape A and B of VDiff for bit reception Edges in the time span from“n₁×tBit-tB”to “n₁×tBit+tA”of signal shape A shall be ignored and shall not cause decoding errors.

5.5.5.4 Wake-up frame evaluation

If all of the following conditions are met,a valid classical CAN frame shall be accepted as a valid WUF. a) The received frame is a classical CAN data frame when DLC matching [see c]in this subclause]is not disabled.The frame may also be a CAN remote frame when DLC matching is disabled. CISO 2024-All rights reserved ISO11898-2:2024(en) No SOF detection Mandatory SOF detection No SOF detection Mandatory SOF detection Figure 11—Mandatory SOF detection after classical CAN frames and error scenarios A wake-up shall be performed when the counter reaches the threshold value or upon the next received WUP. The default threshold value shall be 32,other values may be configured. Up to four (or up to eight when bit rate>500 kbit/s)consecutive classical CAN data frames and CAN remote frames that start after the bias reaction time,tBias,has elapsed can be either ignored(no error counter increase of failure)or judged as erroneous (error counter increase even in case of no error). Receiving a frame in CEFF with non-nominal reserved bits (SRR,r0)shall not lead to an increase of the error counter.

5.5.5.6 Tolerance to CAN FD frames (optional)

After receiving a recessive FD format indicator(FDF)bit followed by a dominant res bit,the decoder unit in the HS-PMA shall wait for nBits_Idle recessive bits before considering a further dominant bit as a start of frame. Figure 11 depicts the position of the mandatory SOF detection when a CANFD data frame is received and in case of an error scenario. Table 21 specifies the valid range for nBits_Idle · Table 21—Number of recessive bits before next SOF

Parameter	Notation	Value	Value
Parameter	Notation	Min.	Max.
Number of recessive bits before a new SOF shall be accepted	nBits_idle	6	10

The behaviour,when the FDF bit is received recessively and the following bit position is also received recessively,is outside the scope of this document. One of the following bitfilter options shall be implemented to support different combinations of arbitration and data phase bit rates. 一 Bitfilter option 1:a data phase bit rate less or equal to four times the arbitration bit rate or 2 Mbit/s, whichever is lower,shall be supported. 一 Bitfilter option 2:a data bit rate less or equal to 10 times the arbitration bit rate or 5 Mbit/s,whichever is lower,shall be supported. CISO 2024-All rights reserved ISO11898-2:2024(en) Dominant signals less than or equal to the minimum of PBitfilter of the arbitration bit time in duration shall not be considered to be a valid bit and shall not restart the recessive bit counter.Dominant signals longerr than or equal to maximum of pBitfilter of the arbitration bit time in duration shall restart the recessive bit counter. Table 22 specifies PBitfite depending on the chosen bitfilter option as percentage of the arbitration bit time. Table 22—Bitfilter in CAN FD data phase

Parameter	Parameter	Parameter	Parameter	Parameter	Parameter	Notation	Notation	Value	Value
Parameter	Parameter	Parameter	Parameter	Parameter	Parameter	Notation	Notation	Min.	Max.
CAN FD	data	phase	bitfilter	(option	1)	PBitfilter	option1	5%	17,5%
CAN FD	data	phase	bitfilter	(option	2)	PBitfilter	option2	2,5%	8,75%

5.5.5.7 Wake-up frame ID evaluation

A CAN-ID mask mechanism shall be provided,in order to exclude ID-bits from the comparison.This mechanism shall support 11-bit and 29-bit identifiers.The IDE bit shall not be part of the ID mask,it shall be evaluated in both cases. NOTE The user selects whether a WUF appears in CBFF or CEFF. All masked ID-bits except“don’t care”shallmatch exactly the configured ID-bits.If the masked ID-bits are configured as“don’t care,then both“1”and“0”shall be accepted.The masking mechanism isimplementation dependent . Figure 12 shows an example for valid WUF IDs corresponding to the ID-mask register. Key d don’t care C care Figure 12—Example for ID masking mechanism CISO 2024-All rights reserved

5.5.5.8 Wake-up frame DLC evaluation

If the DLC matching condition is enabled,then a classical CAN frame can only be a valid WUF when the DLC of the received frame matches exactly the configured DLC. If the DLC matching condition is disabled,then the DLC and data field are not evaluated,and a classical CAN frame is already a valid WUF when the identifier matches (see 5.5.5.7)and the CRC is correct.

5.5.5.9 Wake-up frame data field evaluation

If the DLC matching condition is enabled,then a classical CAN frame can only be a valid WUF if at least one logic 1 bit within the data field of the received WUF matches to a logic 1 bit of the data field within thee configured WUF. If the DLC matching condition is disabled,then the DLC and data field are not evaluated,and a classical CAN frame is already a valid WUF when the identifier matches (see 5.5.5.7)and the CRC is correct. Figure 13 shows an example with a non-matching and a matching ID field. Figure 13—Example of the data field within a received classical CAN data frame

5.5.6 Bus biasing procedure

5.5.6.1 General requirements

The HS-PMA implementation with bus biasing functionality shall comply with the parameters given in Table 3 and Table 4. When the HS-PMA implementation features a low-power mode and selective wake-up,automatic voltage biasing is required.For all other implementation,either normal biasing or automatic voltage biasing shall bee implemented.

5.5.6.2 Normal biasing

Normal biasing means bus biasing is active in normal-power mode and inactive in low-power mode.

5.5.6.3 Automatic voltage biasing

Automatic voltage biasing means bus biasing is active in normal-power mode and is controlled by the differential voltage between CAN_H and CAN_Lin low-power mode. Figure 14 s pecifies the finite state machine for the bus biasing behaviour.When entering state A,the optional timer,twake,shall be reset and restarted;when entering state C or D,the timer,tsilence,shall be reset and restarted. CISO 2024-All rights reserved ISO11898-2:2024(en) On implementation power on 2 3 Implementation enters normal mode Low Power Mode:dominant state>tFiter Normal Mode:dominant state 5 Differential voltage recessive state >tFilter 6 Differential voltage dominant state>tFilter Optional:twake expired Differential voltage recessive state>tFiter Optional:twake expired Differential voltage dominant state >triter tsilence expired AND implementation in low power mode Low Power Mode:recessive state>triter Normal Mode:recessive state mpemcntadono power mode Key

1 Ini state;bus biasing is inactive

2 state A;bus biasing is inactive

3 state B;bus biasing is inactive

4 state C;bus biasing is active

5 state D;bus biasing is active

6 wait state;bus biasing is inactive

Figure 14—Bus biasing control for automatic voltage biasing Table 23specifies the bus biasing control timings and Figure 15the bias reaction time. CISO 2024-All rights reserved ISO11898-2:2024(en) Table 23—HS-PMA bus biasing control timings

Parameter	Notation	Value	Value	Condition
Parameter	Notation	Min.
[μs]	Max.
[μs]	Condition
Timeout for bus inactivity	tsilence	0,6×106	1,2×106	Timer is reset and restarted when bus changes from dominant to recessive or vice versa.
Bus bias reaction time	Bias	Not defined	250,0	Measured from the start ofa domin ant-re- cessive-dominant sequence (each phase 6μs)until vsym≥0,1.See Figure 15vsym as defined in Table 12.

Figure 15—Test signal definition for bias reaction time measurement

6 Conformance

A conformance test plan is not in the scope of this document. Annex B provides an overview of optional features and implementation choices. CISO 2024-All rights reserved ISO11898-2:2024(en) Annex A (normative) HS-PMA with SIC mode and FAST mode A.1 Operating principle During SIC mode the transmitter entity drives a differential voltage between the CAN_H and CANL signals to reflect a logical 0 (dominant)or drive another differential voltage to reflect a logical 1 [recessive].During the signalimprovement time,the potential differential disturbances like reflections from the wiring harness are reduced.During FAST TX mode,the transmitter entity signals a logical 0(level_0)or signals a logical1 (level_ 1).During FAST RXmode,the transmitter entity signals a logical 1(passive recessive)].The signals on CAN_H and CAN_L are building the MDI towards the PMD sublayer. The PMA provides the PWM decoding in accordance with the PWM encoding in the PCS as specified in ISO11898-1. Table A.1shows the possible combinations of PMA operating modes and related states. NOTE CiA 612-2 provides additional information about the PWM coding implementation. Table A.1—PMA operating modes and expected behaviour

Operating mode	Voltage biasing state	Transmitter state	Receiver state
SIC mode	Voltage biasing active	Dominant or recessive	Dominant or recessive
FAST TXmode	Voltage biasing active	level_1 or level_0	level_1 or level_0
FAST RX mode	Voltage biasing active	Passive recessive	level_1 orlevel_0

For the parameters that are not described in Annex A, the specification in Clause5 applies. A.2 Static parameter A.2.1 Recessive output characteristics Table A.2 specifies the passive/active recessive output characteristics when voltage biasing is active. CISO 2024-All rights reserved Table A.2—PMA passive/active recessive output characteristics terminated,voltage biasing active

Parameter a	Notation	Value	Value	Value
Parameter a	Notation	Min.[V]	Nom.[V]	Max.[V]
Single-ended output voltage on CAN_H(based on supply reference voltage)a	VCAN_H	+2,0	+2,5	+3,0
Single-ended output voltage on CAN_Hb	VCAN H rec	2,256	+2,5	+2,756
Single-ended output voltage on CAN_L(based on supply reference voltage)a	VCAN_L	+2,0	+2,5	+3,0
Single-ended output voltage on CAN_Lb	VCANLrec	+2,256	+2,5	+2,756
Differential output voltage	VDiff	-0,5	0	+0,05
NOTE The requirements in this table apply concurrently.Therefore,notall combinations of VCAN_Hand VCAN_Lare compliant with the defined differential output voltage.
a Measurement setup according to Figure 2:
RL>1010Ω
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)
b Measurement setup according to Figure 2:
Load condition in SIC mode:45Ω≤RL≤65Ω(tolerance≤±1%)
C₁=4,7 pF(tolerance≤±5%)
C₂=0pF(not present)
CRxD=0pF(not present)	NOTE The requirements in this table apply concurrently.Therefore,notall combinations of VCAN_Hand VCAN_Lare compliant with the defined differential output voltage.
a Measurement setup according to Figure 2:
RL>1010Ω
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)
b Measurement setup according to Figure 2:
Load condition in SIC mode:45Ω≤RL≤65Ω(tolerance≤±1%)
C₁=4,7 pF(tolerance≤±5%)
C₂=0pF(not present)
CRxD=0pF(not present)	NOTE The requirements in this table apply concurrently.Therefore,notall combinations of VCAN_Hand VCAN_Lare compliant with the defined differential output voltage.
a Measurement setup according to Figure 2:
RL>1010Ω
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)
b Measurement setup according to Figure 2:
Load condition in SIC mode:45Ω≤RL≤65Ω(tolerance≤±1%)
C₁=4,7 pF(tolerance≤±5%)
C₂=0pF(not present)
CRxD=0pF(not present)	NOTE The requirements in this table apply concurrently.Therefore,notall combinations of VCAN_Hand VCAN_Lare compliant with the defined differential output voltage.
a Measurement setup according to Figure 2:
RL>1010Ω
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)
b Measurement setup according to Figure 2:
Load condition in SIC mode:45Ω≤RL≤65Ω(tolerance≤±1%)
C₁=4,7 pF(tolerance≤±5%)
C₂=0pF(not present)
CRxD=0pF(not present)	NOTE The requirements in this table apply concurrently.Therefore,notall combinations of VCAN_Hand VCAN_Lare compliant with the defined differential output voltage.
a Measurement setup according to Figure 2:
RL>1010Ω
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)
b Measurement setup according to Figure 2:
Load condition in SIC mode:45Ω≤RL≤65Ω(tolerance≤±1%)
C₁=4,7 pF(tolerance≤±5%)
C₂=0pF(not present)
CRxD=0pF(not present)

A.2.2 Output characteristics SIC mode and FAST TX mode Table A.3 specifies the voltages that are required for the CAN_L signals. Table A.3—PMA dominant output characteristics during SIC mode

Parametera	Notation	Value a	Value a	Condition
Parametera	Notation	Min.[V]	Max.[V]	Condition
Single-ended voltage on CAN_H	VCANH	3,0	4,26	RL=45Ω to 65Ω
Single-ended voltage on CANL	VCANL	0,75	2,01	RL=45Ω to 65Ω
Differential voltage on normal differen- tial load	VDiff	1,5	3,0	RL=45Ω to 65Ω
Differential voltage on effective resist- ance during arbitration	Viff	as specified in 5.3.4	as specified in 5.3.4	as specified in 5.3.4
Differential voltage on extended differen- tial load range (optional)	Viff	1,5	3,3	RL=45Ωto 70Ω
a Measurement setup according to Figure 2: RL,see “Condition”column in this table C₁=0pF(not present)
C₂=0 pF(not present)
CRXD=0pF(not present)	a Measurement setup according to Figure 2: RL,see “Condition”column in this table C₁=0pF(not present)
C₂=0 pF(not present)
CRXD=0pF(not present)	a Measurement setup according to Figure 2: RL,see “Condition”column in this table C₁=0pF(not present)
C₂=0 pF(not present)
CRXD=0pF(not present)	a Measurement setup according to Figure 2: RL,see “Condition”column in this table C₁=0pF(not present)
C₂=0 pF(not present)
CRXD=0pF(not present)	a Measurement setup according to Figure 2: RL,see “Condition”column in this table C₁=0pF(not present)
C₂=0 pF(not present)
CRXD=0pF(not present)

Table A.4 specifies the voltages that are required on the CAN_H signals. CISO 2024-All rights reserved Table A.4—PMA output characteristics during FAST TX mode

Parametera	Parametera	Notation	Value a	Value a	Condition
Parametera	Parametera	Notation	Min.[V]	Max.[V]	Condition
Single-ended voltage on CAN_H	level_0	VCAN HO	+2,55	+3,51	RL=45Ωto 60Ω
Single-ended voltage on CAN_H	level_1	VCAN H1	+1,50	+2,46	RL=45Ωto 60Ω
Single-ended voltage on CAN_L	level_0	VCANL₀	+1,50	+2,46	RL=45Ωto 60Ω
Single-ended voltage on CAN_L	level_1	VCAN L₁	+2,55	+3,51	RL=45Ωto 60Ω
Differential voltage on nor- mal differential load	level_0	VDiff₀	+0,60	+1,50	RL=45Ωto 60Ω
Differential voltage on nor- mal differential load	level_1	VDiff₁	-1,50	-0,60	RL=45Ωto 60Ω
Measurement setup according to Figure 2: RL,see “Condition”column in this table C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)	Measurement setup according to Figure 2: RL,see “Condition”column in this table C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)	Measurement setup according to Figure 2: RL,see “Condition”column in this table C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)	Measurement setup according to Figure 2: RL,see “Condition”column in this table C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)	Measurement setup according to Figure 2: RL,see “Condition”column in this table C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)	Measurement setup according to Figure 2: RL,see “Condition”column in this table C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)

Figure A.1 illustrates the voltage range for the dominant state during SIC mode. Figure A.2 illustrates the voltage range during FAST TX Mode. a)Voltage range of VCAN_H dominant while PMA is in SIC mode,when VCAN_Lvaries from minimum to maximum voltage level (45-Ω to 65-Ω differential load condition) CISO 2024-All rights reserved ISO11898-2:2024(en) b)Voltage range of VCAN_dominant while PMA is in SIC mode,when VCAN_H varies from minimum to maximum voltage level (45Ωto 65Ωdifferential load condition) Key

1 range of VCANHdominant

2 range of VCAN_Ldominant

VDiff differential voltage between CAN_H and CAN_L wires VCAN_H single-ended voltage on CAN_H wire VCANL single-ended voltage on CAN_L wire Figure A.1—Voltage range of VCAN_Hand VCANL during dominant state while PMA is in SIC mode,when VCANL,VCAN_H,and Vcc vary from minimum to maximum voltage level(45Ωto 65Ω differential load condition) CISO 2024-All rights reserved a )Voltage range of VCAN_L0 and VCAN_L1 while PMA is in FAST TXmode,when VCAN_HO,VCAN_H1, and Vcc vary from minimum to maximum voltage level(45Ωto 60Ω differential load condition) CISO 2024-All rights reserved ISO11898-2:2024(en) b)Voltage range of VCAN_HO and VCAN_H1while PMA is in FAST TXmode,when VCAN_Lo,VCANL₁,and Vcc vary from minimum to maximum voltage level(45Ωto 60Ω differential load condition) Key

1 range of VCAN_H level_0

2 range of VCAN_H level_1

3 range of VCANLlevel_0

4 range of VCAN_Llevel_1

VDiff₀ differential voltage between CAN_H and CAN_L wires,level_0 VDiff₁ differential voltage between CAN_H and CAN_L wires,level_ 1 VCAN_HO single-ended voltage on CAN_H wire,level_0 VCAN_H1 single-ended voltage on CAN_H wire,level_ 1 VCANL0 single-ended voltage on CAN_L wire,level_0 VCANL1 single-ended voltage on CAN_L wire,level_ 1 Figure A.2—Voltage range of VCAN_Land VCAN_H while PMA is in FAST TX mode A.2.3 PMA driver output current in FAST TX mode Table A.5 specifies the PMA driver output current in FAST TX mode. CISO 2024-All rights reserved Table A.5—PMA driver output current in FAST TX mode

| Parametera | Notation | Value(max.) [mA] | Condition | |---|---|---|---| | Absolute current on CAN_H | ICANH | 115 | -3V≤VCAN_H≤+18V | | Absolute current on CAN_L | IcANL | 115 | -3V≤VCANL≤+18V | | a Measurement setup according to Figure 2 with either VcAN_H or VCAN_L enforced to voltage levels as mentioned in the conditions by connection to an external voltage source. RL>1010Ω(not present) C₁=0 pF(not present) C₂=0pF(not present) CRxD=0pF(not present) | a Measurement setup according to Figure 2 with either VcAN_H or VCAN_L enforced to voltage levels as mentioned in the conditions by connection to an external voltage source. RL>1010Ω(not present) C₁=0 pF(not present) C₂=0pF(not present) CRxD=0pF(not present) | a Measurement setup according to Figure 2 with either VcAN_H or VCAN_L enforced to voltage levels as mentioned in the conditions by connection to an external voltage source. RL>1010Ω(not present) C₁=0 pF(not present) C₂=0pF(not present) CRxD=0pF(not present) | a Measurement setup according to Figure 2 with either VcAN_H or VCAN_L enforced to voltage levels as mentioned in the conditions by connection to an external voltage source. RL>1010Ω(not present) C₁=0 pF(not present) C₂=0pF(not present) CRxD=0pF(not present) |

A.2.4 Static receiver input characteristics,voltage biasing active,FAST RX mode or FAST TX mode The receiver uses the transmitter output signals CAN_H and CAN_Las differential input. Table A.6specifies the PMA static parameter input characteristics,voltage biasing active,FAST RX mode,and FAST TX mode parameters.This applies to the PMA implementation,when itis in FAST TXmode or FASTRXmode.The VDiff differential input voltage ranges represent level_0 respectively level_ 1. Table A.6—PMA static receiver input characteristics,voltage biasing active,FAST RXmode or FAST TX mode

Parametera	Notation	Value	Value	Condition
Parametera	Notation	Min.[V]	Max.[V]	Condition
Level_0 state differential input voltage range	VDiff	+0,1	+8,0	-12,0V≤VCAN L
VCAN_H≤+12,0V
Level_1 state differential input voltage range	VDiff	-8,0	-0,1	-12,0V≤VCAN L
VCAN_H≤+12,0V
a Measurement setup according to Figure 2: RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0 pF(not present)	a Measurement setup according to Figure 2: RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0 pF(not present)	a Measurement setup according to Figure 2: RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0 pF(not present)	a Measurement setup according to Figure 2: RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0 pF(not present)	a Measurement setup according to Figure 2: RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0 pF(not present)

Figure A.3 illustrates Table A.6. CISO 2024-All rights reserved ISO11898-2:2024(en) VCAN H. VCANL=+8V +1V

• 11V -9V -12V -10V 8V-7V-6V-5V-4V-3V-2V- 1V × VCAN H-VCANL=+100mV VCAN_H +12V +11V +10V +9V +8V +7V +6V +5V +4V +3V +2V 2V 1V -2V -3V -4V -5V 1 2 3V 4V 5V 6V 7y8V 9V 10V 今 VCAN_L 11V 12V VCANL VCANH— V Key -7V+ -8V -9V -10V -11V -12V

1 range of VCAN_HRXD=0

2 range of VCAN_H RXD=1

VDiff=VCAN_H-VCANL differential voltage between CAN_H and CAN_L wires VCAN_H VCANL single-ended voltage on CAN_H wire single-ended voltage on CAN_L wire Figure A.3—PMA static receiver input characteristics,voltage biasing active,PMA in FAST RXmode or FAST TX mode (condition-12,0V≤VCAN_L,VCAN_H≤+12,0V,+4,75V≤Vcc≤+5,25V) A.2.5 Out-of-bounds(00B)comparator The 0OB comparator uses the signals CAN_H and CANL as differential input. Figure A.4 specifies how the 00B and the comparator signals are linked with the RXD in SIC mode.The“&”(AND)gate is illustrating thee logical function,how the O0B signal is merged into the RXD line for the CAN XL use case with FAST level schemes when the PMA implementation is in SIC mode as a receiving node. ◎ ISO 2024-All rights reserved Comp CAN_H RXD CAN_L 00B Figure A.4—0OB and comparator signals when RXD is in SIC mode Table A.7 specifies the OOB high state and OOB low state differential input voltage ranges,when the PMA implementation is in SIC mode and voltage biasing is active. Table A.7—PMA static 0OB input characteristics(voltage biasing active;SIC mode)

Parametera	Notation	Value	Value	Condition
Parametera	Notation	Min.[V]	Max.[V]	Condition
Low state differential input voltage range	VDiff	-8,0	-0,45	-12V≤VCAN_L,VCAN_H≤+12V
High state differential input voltage range	VDiff	-0,25	+8,0	-12V≤VCAN_L,VCAN_H≤+12V
Measurement setup according to Figure 2: RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)	Measurement setup according to Figure 2: RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)	Measurement setup according to Figure 2: RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)	Measurement setup according to Figure 2: RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)	Measurement setup according to Figure 2: RL>1010Ω(not present)
C₁=0pF(not present)
C₂=0pF(not present)
CRxD=0pF(not present)

Figure A.5 illustrates the PMA static comparator receiver input characteristics(voltage biasing active,SIC mode]. Figure A.6 illustrates the PMA static OOB receiver input characteristics (voltage biasing active,SIC mode].Figure A.7 illutrates the PMA static comparator and the OOB receiver input characteristics (voltage biasing active;SIC mode). CISO 2024-All rights reserved ISO11898-2:2024(en) VcAN AN H” -11V -9V VCAN_H +12V +11V +10V +9V +8V +7V +6V +5V +4V +3V +2V +1V VCAN_H-VCANL=500 mV VCANL 1 2 11V -12V -10V 8V-7V-6V-5V-4V-3V-2y - 1V 2V 3V 4V 5V 6V 8V 9V 10V 12V VCANL -2V -3V -4V -5V -6V -7V 8V -9V -10V -11V -12V VcANL Key

1 range of VCAN_H,RXD=0

2 range of VCAN_H,comparator output=1

VDiff=VCAN_H-VCANL differential voltage between CAN_H and CAN_L wires VCAN_H single-ended voltage on CAN_H wire VCANL single-ended voltage on CAN_L wire Figure A.5—PMA static comparator receiver input characteristics (voltage biasing active;SIC mode;conditions:-12,0V≤VCANL,VCAN_H≤+12,0V,+4,75V≤Vcc≤+5,25V) CISO 2024-All rights reserved ISO11898-2:2024(en) -11V -9V -12V -10V VcANL Key

1 2

VDiff=VCAN_H-VCANL VCAN_H VCANL

| VCANH-VCANL=+8V

90-7V-6V-5V-4V-3V-2V

cAN

CAN | VCANH +12V +11V +10V 1 +9V *8V +7V +6V +5V +4V +3V +2V +1V

2V 3V 4V 5V 6V 4-1V -2V -3V -4V -5V -6V -7V- -8V -9V -10V -11V -12V | VCANL

VCAN_H-VCANL=-250mV

2

11V 7y8V 9V 10V 12V VCANL | |---|---|---|

range of VCAN_H,0OB output=1 range of VCAN_H,0OB output=0 differential voltage between CAN_H and CAN_L wires single-ended voltage on CAN_H wire single-ended voltage on CAN_L wire Figure A.6—PMA static OOB receiver input characteristics(voltage biasing active;SIC mode; conditions:-12,0V≤VCAN_L,VCAN_H≤+12,0V,+4,75V≤Vcc≤+5,25V) CISO 2024-All rights reserved ISO11898-2:2024(en)

| Key

1	range of VCAN_H,RXD=0
2	range of VCAN_H,RXD=1
VDif=VCAN_H-VCANL	differential voltage between CAN_H and CAN_L wires
VCANH	single-ended voltage on CAN_H wire
VCANL	single-ended voltage on CAN_L wire

Figure A.7—PMA static comparator and OOB receiver input characteristics,voltage biasing active, SIC mode (condition-12,0V≤VCAN_L,VCAN_H≤+12,0V,+4,75V≤Vcc≤+5,25V) A.2.6 TXD input signal characteristic(normal-power mode) The TXD signal input characteristic shall be applied to PMA implementations only if PMA implementations provide this input signal as a physically available signal. Figure A.8 specifies the TXD input circuitry. The TXD input of the PMA implementation shall provide a symmetrical input impedance,which follows the input voltage level through a repeater functionality in normal-power mode.In case the TXD input level rises above the threshold VTXDThresh as specified Table A.8, a pull-up behaviour towards the interface supply rail V¹o shall become active.In case the TXD input level falls below the threshold V(TXD)Thresh as specified in Table A.8, a pull-down behaviour towards GND shall become active.V₁n may be equal to Vcc and shall be assigned to the interface supply rail of the connected driving device (e.g.the CAN protocol controller that implements the DLL].The PMA implementation shall have an input impedance as specified in Table A.8. Furthermore,the input impedance shall meet the requirement specified in Table A.8. ◎ ISO 2024-All rights reserved ISO11898-2:2024(en) Figure A.8—TXD input circuitry Table A.8—PMA TXD input characteristics

Parameter	Notation	Value	Value	Remark
Parameter	Notation	Min.	Max.	Remark
TXD input threshold volt- age	V(TXD)Thresh	0,95(V¹0/2)V	1,05(V¹0/2)V	Within V¹o specification range In this range the detection chang- es from low to high or vice versa.
TXD input low voltage range	V(TXD)Low	GND	V(TXDThresh_min	Within V¹o specification range In this range the TXD input level is detected as low.The min value can be below GND in accordance with the PMA implementations.
TXD input high voltage range	VCTXD)High	V(TXDThresh_max	V¹o	Within V₁o specification range In this range the TXD input level is detected as high.The max
value can be above V¹oin accord- ance with the PMA implementa-
tions.
Pull-up and pull-down impedance	R(TXD)PU
RCTXDPD	20kΩ	80 kΩ	Within V¹o specification range
Pull-up and pull-down impedance matchinga	mR(TXD)	-0,05	+0,05	Within V1o specification range
a The matching shall be calculated as mR(TXD)=2×(RTXDPU-RCTXDPD)/(RTXDPu+RCTXDPD).	a The matching shall be calculated as mR(TXD)=2×(RTXDPU-RCTXDPD)/(RTXDPu+RCTXDPD).	a The matching shall be calculated as mR(TXD)=2×(RTXDPU-RCTXDPD)/(RTXDPu+RCTXDPD).	a The matching shall be calculated as mR(TXD)=2×(RTXDPU-RCTXDPD)/(RTXDPu+RCTXDPD).	a The matching shall be calculated as mR(TXD)=2×(RTXDPU-RCTXDPD)/(RTXDPu+RCTXDPD).

A.3 Dynamic parameter A.3.1 PMA driver symmetry FAST TX mode In order to achieve a level of the RF emission that is acceptably low,the transmitter shall meet the driver signal symmetry in SIC mode and in FAST TX mode as specified in Table A.9. CISO 2024-All rights reserved ISO11898-2:2024(en) Table A.9—PMA driver symmetry

Parametera	Notation	Value b	Value b
Parametera	Notation	Min.	Max.
Driver symmetrya	Vsym	0,95	1,05
a Vsym=(VCANH+VcAN_LJ/Vree Vrec=VCAN_H_rec+VAN_L_rec
b Measurement setup according to Figure 2:
Load condition in SIC mode:45Ω≤RL≤65Ω
Load condition in FAST RXmode or FAST TXmode:45Ω≤RL≤60Ω C₁=4,7nF (tolerance≤±5%)
C₂=0pF(not present)
CRxD=0pF(not present)	a Vsym=(VCANH+VcAN_LJ/Vree Vrec=VCAN_H_rec+VAN_L_rec
b Measurement setup according to Figure 2:
Load condition in SIC mode:45Ω≤RL≤65Ω
Load condition in FAST RXmode or FAST TXmode:45Ω≤RL≤60Ω C₁=4,7nF (tolerance≤±5%)
C₂=0pF(not present)
CRxD=0pF(not present)	a Vsym=(VCANH+VcAN_LJ/Vree Vrec=VCAN_H_rec+VAN_L_rec
b Measurement setup according to Figure 2:
Load condition in SIC mode:45Ω≤RL≤65Ω
Load condition in FAST RXmode or FAST TXmode:45Ω≤RL≤60Ω C₁=4,7nF (tolerance≤±5%)
C₂=0pF(not present)
CRxD=0pF(not present)	a Vsym=(VCANH+VcAN_LJ/Vree Vrec=VCAN_H_rec+VAN_L_rec
b Measurement setup according to Figure 2:
Load condition in SIC mode:45Ω≤RL≤65Ω
Load condition in FAST RXmode or FAST TXmode:45Ω≤RL≤60Ω C₁=4,7nF (tolerance≤±5%)
C₂=0pF(not present)
CRxD=0pF(not present)

A.3.2 PMA transmit timeout SIC mode In SIC mode the PMA implementation shall limit the duration of dominant transmission as specified in Table A.10, in order to prevent a permanent dominant clamping condition when the TXD input is permanently asserted. Table A.10—PMA transmit timeout

Parameter	Notation	Value	Value
Parameter	Notation	Min.[ms]	Max.[ms]
Transmit dominant timeout	tdom	0,80	6,0

A.3.3 Transmitter,receiver and OOB timing behaviour The timing parameters specified in Table A.11,Table A.12,Table A.13, and Table A.14 shall be measured at the RXD output and the TXD input of the PMA implementation as well as on the differential voltage between CAN_H and CANL. Table A.11 specifies the loop delay requirement for SIC mode. Table A.12 and Table A.13 specify the data signal timing requirements during SIC mode and during FAST RX or FAST TX Mode. Table A.14 specifies the propagation delay symmetry requirements during mode transition. For the impedance specification see Table 9. For measuring the timing in the signal traces, Figure A.9 specifies the timing diagram during SIC mode; Figure A.10 illustrates the timing diagram during FAST TX mode and PWM driven; Figure A.11 illustrates the PMA OOB implementation timing diagram during SIC mode and PWM driven; Figure A.12 illustrates the timing diagram in the transition from SIC mode to FAST TXmode;Figure A.13 illustrates the timing diagram in the transition from FAST TX mode to SIC mode; Figure A.14 illustrates the SIC mode time after FAST RX detection; Figure A.15 illustrates the propagation delay symmetry in the mode transition. CISO 2024-All rights reserved ISO11898-2:2024(en) Figure A.9—PMA implementation timing diagram,during SIC mode a)Overview timing diagram in FAST TX mode b)Symmetry of level_1 timing diagram in FAST TXmode Figure A.10—PMA implementation timing diagram,during FAST TX mode,PWM driven CISO 2024-All rights reserved ISO11898-2:2024(en) The delay from TXD to the CAN_H and CAN_Lin FAST TX Mode as shownin Figure A.10 a)shall be measured from the rising TXD edge of the PWM symbol forcing the according level change on CAN_H and CAN_L. Figure A.11—PMA 0OB implementation timing diagram,during SIC mode,PWM driven NOTE Figure A.11 illustrates the timing behaviour on RXD of a receive node in SIC mode while another node is sending in FAST TX mode.Eventually,the 00B comparator output signal is not physically available to the outside of a transceiver.Therefore,Figure A.11 illustrates the transceiver internal 00B signal and how it is reflected later in length on the RXD pin of a receiving node in SIC mode. Figure A.12—PMAimplementation timing diagram,transition SIC mode to FAST TXmode,PWM driven CISO 2024-All rights reserved ISO11898-2:2024(en) Key

1 receiver threshold range FAST mode

2 receiver threshold range SIC mode

3 active recessive

4 passive recessive

Figure A.13—PMAimplementation timing diagram,transition FAST TXmode to SIC mode,PWM driven Figure A.14—PMA implementation timing diagram,SIC mode time after FAST RX detection Table A.11—PMA implementation loop delay requirement for SIC mode CISO 2024-All rights reserved ISO11898-2:2024(en) Table A.12—PMA implementation data signal timing requirements,during SIC mode

Parametera	Notation	Value	Value	Remark
Parametera	Notation	Min.
[ns]	Max.
[ns]	Remark
Signal improvement time	tsiIc	+300	+530	Time from rising edge of the TXD signal to the end of the signal improvement phase
Transmitted bit width variation	t△Bit(Bus)	-10	+10	Bus recessive bit length variation relative to TXD bit length,see Figure A.9
t△Bit(Bus)=Bit(Bus)-Bit(TXD)
Received bit width variation	t△Bit(RXD)	-30	+20	RXD recessive bit length variation relative to TXD bit length,see Figure A.9
t△Bit(RXD)=tBit(RXD)-BitC(TXD)
Receiver timing sym- metry	t△REC	-20	+15	RXD recessive bit length variation relative to bus bit length,see Figure A.9
t△REC=Bit(RXD)-Bit(Bus)
Propagation delay
from TXD logical 0 to bus dominant	tProp(TXD-BusDom)	not de-
fined	+80	See Figure A.9
Propagation delay
from TXD logical 1 to bus recessive	tprop(TXD-BusRec)	not de-
fined	+80	See Figure A.9
Propagation delay of the receiver from bus to RXD logical 0	tProp(BusDom-RXD)	not de-
fined	+110	See Figure A.9
Propagation delay of the receiver from bus to RXD logical 1	tProp(BusRec-RXD)	not de-
fined	+110	See Figure A.9
RXD low pulse width
during fast data
trafficb,at the bit rate 10 Mbit/s	tooB_LOW(RXD)	+30	not de-
fined	Bit(TXD)=100 ns see Figure A.11
RXD low pulse width
during fast data
trafficb,at the bit rate 20 Mbit/s	tooB_LOW(RXD)	+15	not de-
fined	Bit(TXD)=50ns
see Figure A.11
a Measurement setup according to Figure 2:
45Ω≤RL≤65Ω
C₁=0 pF(not present)
C₂=100 pF (tolerance≤±1%)
CRXD=15 pF (tolerance≤±1%)
Measurement according to Figure A.9:
The input signal on TXD shall have rising times(10%to 90 %)and fall times(90 %to 10 %)of less than 10ns with n=1 to 5.
b Measured through FAST TX mode sending with associated data bit rate while accessing the 0OB comparator through a dedicated test mode(semiconductor-manufacturer specific).
Measurement setup according to Figure 2 for FAST TX mode:
4,75V≤Vcc≤5,25V
45Ω≤RL≤60Ω
C₁=0 pF
C₂=25 pF
CRXD=15pF	a Measurement setup according to Figure 2:
45Ω≤RL≤65Ω
C₁=0 pF(not present)
C₂=100 pF (tolerance≤±1%)
CRXD=15 pF (tolerance≤±1%)
Measurement according to Figure A.9:
The input signal on TXD shall have rising times(10%to 90 %)and fall times(90 %to 10 %)of less than 10ns with n=1 to 5.
b Measured through FAST TX mode sending with associated data bit rate while accessing the 0OB comparator through a dedicated test mode(semiconductor-manufacturer specific).
Measurement setup according to Figure 2 for FAST TX mode:
4,75V≤Vcc≤5,25V
45Ω≤RL≤60Ω
C₁=0 pF
C₂=25 pF
CRXD=15pF	a Measurement setup according to Figure 2:
45Ω≤RL≤65Ω
C₁=0 pF(not present)
C₂=100 pF (tolerance≤±1%)
CRXD=15 pF (tolerance≤±1%)
Measurement according to Figure A.9:
The input signal on TXD shall have rising times(10%to 90 %)and fall times(90 %to 10 %)of less than 10ns with n=1 to 5.
b Measured through FAST TX mode sending with associated data bit rate while accessing the 0OB comparator through a dedicated test mode(semiconductor-manufacturer specific).
Measurement setup according to Figure 2 for FAST TX mode:
4,75V≤Vcc≤5,25V
45Ω≤RL≤60Ω
C₁=0 pF
C₂=25 pF
CRXD=15pF	a Measurement setup according to Figure 2:
45Ω≤RL≤65Ω
C₁=0 pF(not present)
C₂=100 pF (tolerance≤±1%)
CRXD=15 pF (tolerance≤±1%)
Measurement according to Figure A.9:
The input signal on TXD shall have rising times(10%to 90 %)and fall times(90 %to 10 %)of less than 10ns with n=1 to 5.
b Measured through FAST TX mode sending with associated data bit rate while accessing the 0OB comparator through a dedicated test mode(semiconductor-manufacturer specific).
Measurement setup according to Figure 2 for FAST TX mode:
4,75V≤Vcc≤5,25V
45Ω≤RL≤60Ω
C₁=0 pF
C₂=25 pF
CRXD=15pF	a Measurement setup according to Figure 2:
45Ω≤RL≤65Ω
C₁=0 pF(not present)
C₂=100 pF (tolerance≤±1%)
CRXD=15 pF (tolerance≤±1%)
Measurement according to Figure A.9:
The input signal on TXD shall have rising times(10%to 90 %)and fall times(90 %to 10 %)of less than 10ns with n=1 to 5.
b Measured through FAST TX mode sending with associated data bit rate while accessing the 0OB comparator through a dedicated test mode(semiconductor-manufacturer specific).
Measurement setup according to Figure 2 for FAST TX mode:
4,75V≤Vcc≤5,25V
45Ω≤RL≤60Ω
C₁=0 pF
C₂=25 pF
CRXD=15pF

CISO 2024-All rights reserved ISO11898-2:2024(en) Table A.13—PMA implementation data signal timing requirements,during FAST RX mode or FAST TX mode

| Parametera | Notation | Min. [ns] | Max. [ns] | Remark | |---|---|---|---|---| | Signal improvement time in FAST TX Mode | tsic_data | not de- fined | +775 | Time from rising edge of TXD symbol to the end of the signal improvement phase,see Figure A.13 | | SIC mode time after FAST RX detection | tsIC_Fast_RXD_Dis | not de- fined | +80 | Time starting with the second falling edge that is used for PWM detection see Figure A.14 | | Transmitted level_1 bit width variation in FAST TX Mode | t△Bit(Bus)Level1 | -5 | +5 | Bus level_1 bit length variation relative to TXD tBit_datalength,see Figure A.10 b) tABit(BusLevel1=tBit(BuSLevel1-ktBit data | | Received logical 1 bit width variation in FAST TX Mode | t△Bit(R×DLogical1 | -10 | +10 | RXD logical 1 bit length variation relative to TXD Bit_datalength,see Figure A.10 b) taBit(R×DLogical1=tBitCRXDLogical1-ktBit data | | Logical 1 receiver timing symmetry in FAST RX Mode | t△REC_Logical1 | -5 | +5 | RXD logical 1 bit length variation relative to bus level_1 bit length,see Figure A.10 b) tAREC Logicall=BiLTRXDLogical-BitCBusSLevel1 | | Propagation delay from mode change to bus level_0 | tprop(BusDom-BusLev- el0) | not de- fined | +80 | See Figure A.12 | | Propagation delay from mode change to bus recessive in FAST TX and FAST RX Mode | tProp(BusLevel0-Rec) | not de- fined | +325 | See Figure A.13 | | Propagation delay from TXD logical 0 to bus level_0 | tProp(TXD-BusLevel0) | not de- fined | +80 | See Figure A.10 a) | | Propagation delay from TXD logical 1 to bus level_1 | tProp(TXD-BusLevel1) | not de- fined | +80 | See Figure A.10 a) | | Propagation delay from bus level_0 to RXD logical0 | tProp(BusLevel0-RXD) | not de- fined | +110 | See Figure A.10 a) | | Propagation delay from bus level_1 to RXD logical 1 | tProp(BusLevel1-RXD) | not de- fined | +110 | See Figure A.10 a) | | Fall time VDiff | tBusfall | +6 | +20 | See Figure A.10 a) | | Rise time Vpiff | tBusrise | +6 | +20 | See Figure A.10 a) | | a Measurement setup according to Figure 2: 45Ω≤RL≤60Ω C₁=0 pF(not present) C₂=25pF(tolerance≤±1%) CRXD=15 pF(tolerance≤±1%) | a Measurement setup according to Figure 2: 45Ω≤RL≤60Ω C₁=0 pF(not present) C₂=25pF(tolerance≤±1%) CRXD=15 pF(tolerance≤±1%) | a Measurement setup according to Figure 2: 45Ω≤RL≤60Ω C₁=0 pF(not present) C₂=25pF(tolerance≤±1%) CRXD=15 pF(tolerance≤±1%) | a Measurement setup according to Figure 2: 45Ω≤RL≤60Ω C₁=0 pF(not present) C₂=25pF(tolerance≤±1%) CRXD=15 pF(tolerance≤±1%) | a Measurement setup according to Figure 2: 45Ω≤RL≤60Ω C₁=0 pF(not present) C₂=25pF(tolerance≤±1%) CRXD=15 pF(tolerance≤±1%) |

CISO 2024-All rights reserved ISO11898-2:2024(en) Table A.14—PMA implementation propagation delay symmetry requirements,during mode transition

| Parametera | Notation | Min. [ns] | Max. [ns] | Remark | |---|---|---|---|---| | Transmitter propagation delay symmetry ADS/DAS | t△Bit(Bus)ADS/DAS | -30 | +30 | see Figure A.15 t△Bit(Bus)ADS/DAS=tprop(TXD-BusDom) tProp(TXD-BusLevel0) | | Receiver propagation delay symmetry ADS/DAS | t△Bit(RXD)ADS/DAS | -20 | +20 | see Figure A.15 t△Bit(RXD)ADS/DAS=tprop(BusDom-RXD)- tProp(BusLevel0-RXD) | | a Measurement setup according to Figure2: 4,75 V≤Vcc≤5,25V 45Ω≤R≤60Ω C₁=0 pF C₂=25 pF CRXD=15pF | a Measurement setup according to Figure2: 4,75 V≤Vcc≤5,25V 45Ω≤R≤60Ω C₁=0 pF C₂=25 pF CRXD=15pF | a Measurement setup according to Figure2: 4,75 V≤Vcc≤5,25V 45Ω≤R≤60Ω C₁=0 pF C₂=25 pF CRXD=15pF | a Measurement setup according to Figure2: 4,75 V≤Vcc≤5,25V 45Ω≤R≤60Ω C₁=0 pF C₂=25 pF CRXD=15pF | a Measurement setup according to Figure2: 4,75 V≤Vcc≤5,25V 45Ω≤R≤60Ω C₁=0 pF C₂=25 pF CRXD=15pF |

CISO 2024-All rights reserved ISO11898-2:2024(en)

3 active recessive

4 passive recessive

Figure A.15—PMA implementation propagation delay symmetry A.3.4 PMA mode selection and decoding The PMA mode selection shall be available through a PWM-coded TXD input signal.Similar edges of thee TXD signal with a period time of shorter than tsymbolNom shall switch the mode of the PMA towards FAST RX mode or FAST TX mode. Consecutive TXD signal period times (logical 0 or logical 1)longer than tFastToSIc during FAST RX mode or FAST TX mode shall switch the mode of the PMA towards the SIC mode. The PMA shall provide the following behaviours: 1)FAST TX mode (for the sending node); 2)FAST RX mode(for all receiving nodes). The PMA shall distinguish the required behaviour based on the last received bit level on pin TXD without PWM encoding.FAST TX mode shall be preselected,if there is a consecutive logical 0 on pin TXD detected for tselect.FAST RX shall be preselected,if there is a consecutive logical 1 on pin TXD detected for tselect: Based on the preselected mode the PMA shall execute the mode transition with the first detected PWM symbol. Table A.15 specifies the timing requirements of the PMA mode selection. Figure A.16 specifies the PMA mode selection through PWM symbols. Table A.15—PMA mode selection timing requirements

| Parameter | Notation | Min. [ns] | Max. [ns] | Remark | |---|---|---|---|---| | PWM symbol acceptance lengtha | tsymbolNom | 45 | 205 | Time between two rising edges on TXD if FAST TXmode is preselected. Time between two falling edges on TXD if FAST RXmode is preselected. PMA implementations can support shorter tsymbolNom periods than 45 ns. | | FAST to SIC mode switching time a | tFastToSIC | 210 | 245 | Time after last symbol edge on TXD | | PWM ratio detected as logical_0 FAST TX | tLogicalL0_Tx | tDecode | 0,5tsymbol- Nom-tDecode | PWM ratio detected as logical_0 in FAST TX mode | | PWM ratio detected as logical_1 FAST TX | tLogical_1_TX | 0,5tsymbol- Nom+tDecode | tsymbolNom- tDecode | PWM ratio detected as logical_1 in FAST TX mode | | PWM ratio detected FAST RX | tLogical_Rx | tDecode | tsymbolNom- tDecode | PWM ratio detected in FAST RXmode | | Mode pre-selection time | tselect | 500 | 980 | Consecutive received bit level time for prese- lection of the required FAST RX mode or FAST TXmode. | | PWM detection resolu- tion | tDecode | Not defined | 5 | Granularity of TXD symbol decoding | | a Up to 205ns,it reads as PWM-coded signals and starting from 250 ns the signals are NRZ-coded (8 Mbit/s). | a Up to 205ns,it reads as PWM-coded signals and starting from 250 ns the signals are NRZ-coded (8 Mbit/s). | a Up to 205ns,it reads as PWM-coded signals and starting from 250 ns the signals are NRZ-coded (8 Mbit/s). | a Up to 205ns,it reads as PWM-coded signals and starting from 250 ns the signals are NRZ-coded (8 Mbit/s). | a Up to 205ns,it reads as PWM-coded signals and starting from 250 ns the signals are NRZ-coded (8 Mbit/s). |

CISO 2024-All rights reserved ISO11898-2:2024(en) TXD Key 50% -tselect 工 50% 2 tsymbolNom 50% 4

1 FAST TX mode pre-selection

2 FAST RX mode pre-selection

3 FAST TX mode level_0

4 FAST RX mode

Figure A.16—Mode selection through PWM As specified in Figure A.16, if FAST RX mode is preselected,the PMA shall detect the PWM signal based on falling edges on the TXD signal;if FAST TX mode is preselected,the PMA shall detect PWM signals based on rising edges on the TXD signal The high to low ratio of consecutive TXD symbols between two rising edges shall be used during FAST TX Mode to distinguish between level_0 and level_ 1. In case the TXD signal between two rising edges is logical 1 for more than 50 %of tsymbolNom,the PMA in FAST TX mode outputs a level_ 1 signal with the detected rising edge.In case the TXD signal between two rising edges is logical 0 for more than 50 %of tsymbolNom,the PMA in FAST TX mode outputs a level_0 signal with the detected rising edge. The PMA shall detect and decode PWM symbols from the TXD signal with a PWM detection resolution tDecode as specified in Table A.15.Figure A.17 specifies the worst-cases how to decode the PWM symbols correctly.If FAST TXmode is preselected or during FAST TX mode a PWM duration between tDecode and 0,5×tsvmholNom -tDecode shallbe detected as logical 0 and cause a level_0 on the bus as specified in Figure A.17 a).If FAST TX mode is preselected or during FAST TX mode a PWM duration between 0,5×tsvmbalNom-tnecode shall be detected as logical 1 and cause a level_ 1 on the bus as specified in Figure A.17 b).If FAST RX mode is preselected or during FAST RX mode a PWM duration between tnecode and tsvmhalNom-tnecode shall be detected as valid symbol as specified in Figure A.17 c).The PWM symbol has no logical value,because any PWM symbol is allowed for the receiving node. a)Transmitting PMA worst-case level_0 PWM symbol to be decoded CISO 2024-All rights reserved

50 %

ISO11898-2:2024(en) —tsymbolNom— tpecode

2 50%

logical_ 1 tpecode

50 %

50% —0,5tsymbolNom→ ——0,5tsymbolNom— b)Transmitting PMA worst-case level_1 PWM symbol to be decoded c)Receiving PMA worst-case PWM symbol Key

1 detection area of logical_0

2 detection area of logical_ 1

3 detection area

Figure A.17—Worst-case level_0 and level_1 PWM symbol to be decoded A.4 Wake-up from low-power mode A.4.1 Via wake-up pattern Upon receiving two consecutive dominant states each for duration of at least tFilter separated by a recessive state of at least triter and followed by a recessive state with duration of at least trilter a wake-up event shall be signalled.The bus biasing can be activated. CISO 2024-All rights reserved 1 2 3 4

7 5

Differential voltage recessive state>titer 6 Differential voltage dominant state>triter twake expired Differential voltage recessive state>rniter twake expired Differential voltage dominant state >triter twake expired Differential voltage recessive state>triter Implementation enters low power mode triter timer resetted Key

1 INI state:no wake-up detected

2 state A:no wake-up detected

3 state B:no wake-up detected

4 state C:no wake-up detected

5 state D:wake-up detected-entering this state shall signal the bus wake-up event and may turn on the bias through implementation-specific measures

6 wait state

7 transition from other nodes;PMA implementation enters normal mode

8 power on

Figure A.18—Wake-up pattern The finite state machine in Figure A.18 specifies the voltage wake-up behaviour for all operation modes. When entering state A,the optional timer twake shall be reset and restarted. Table A.16 specifies the voltage wake-up control timings. Figure A.19 illustrates the test signal definition for bus wake-up reaction time measurement.Figure A.20 illustrates the test signal definition for extended ◎ ISO 2024-All rights reserved ISO11898-2:2024(en) dominant pulse.Figure A.21 illustrates the test signal definition for single dominant pulse.Figure A.22 illustrates the test signal definition for single and extended dominant pulse. Table A.16—PMA voltage wake-up control timings

Parameter	Notation	Value	Value	Condition
Parameter	Notation	Min.[μs]	Max.[μs]	Condition
CAN activity filter time,long	tFilter(long)	0,50	1,45	Network voltage according to
Table B.2
CAN activity filter time,short	Filter(short)	0,15	0,95	Network voltage according to
Table B.2
Wake-up timeout	twake	as specified in Table 20	as specified in Table 20	as specified in Table 20
Wake-up pattern signalling	tFlag	not defined	250,0	Measured from the completed wake- up pattern,see Table A.13

工	2	3	4	6	7
5	5	5	5	6	7

Key

1 INI state

2 state A

3 state B

4 state C

5 low-power mode

6 wake-up pattern detected

7 wake flagged

Figure A.19—Test signal definition for bus wake-up reaction time measurement,wake-up timeout twake CISO 2024-All rights reserved ISO11898-2:2024(en) VDiff 2V 1,15V 0,4V t>tFilter(max) t>twake t>EFnutermax)

2 3

4 Key

1 INI state

2 state A

3 wait state

4 low-power mode

Figure A.20—Test signal definition for extended dominant pulse

1 2 3 1 4

Key

1 INI state

2 state A

3 state B

4 low-power mode

Figure A.21—Test signal definition for single dominant pulse CISO 2024-All rights reserved ISO11898-2:2024(en)

2 3 4 5

6 Key

1 INI state

2 state A

3 state B

4 state C

5 wait state

6 low-power mode

Figure A.22—Test signal definition for single and extended dominant pulses CISO 2024-All rights reserved ISO11898-2:2024(en) Annex B (informative) ECU and network design B.1 Implementation options This clause specifies the PMA sublayer.It can be implemented in a stand-alone CAN transceiver chip or in a system basis chip comprising additional functionality,e.g voltage regulators,wake-up logic and watchdog These implementations can also provide additional functions,which are outside the scope of this document. Figure B.1 shows optional functions and their relation to OSI sublayers.One is an optional digital processing unit,which hides CAN FD data frames to the CAN data link layer implementation.Another optional feature is a galvanic isolation. NOTE1 These optional functions cause some timing delays. Attachment unit interface(AUI e.g.transceiver or systemi base chip implementation Physical CAN_H frame attach- ment (PMA) sub- layer Media dependent interface(MDI) Figure B.1—Optional functions and their relation to OSI sublayers Figure B.1 shows also some optional functionality belonging to the PMD sublayer.This includes,for example, a ringing suppression circuitry.These optional functionalities can improve the signal integrity of thee analogue signals on the bus wires(CAN_L’and CAN_H’). NOTE 2 These functions can have impacts on the EMC performance. When implementing a ringing suppression circuitry,the differential internal resistance is typically 100Ωin a bit-width interval [tBit(Bus]after the dominant-to-recessive edge. B.2 Expectations on a CAN network This clause outlines which input voltages on VCAN_L and VCAN_H are recommended for proper operation of HS-PMA implementations connected to a medium. Table B.1 shows the CAN interface voltage parameters for the reception of recessive state. CISO 2024-All rights reserved Table B.1—Input voltage parameters for reception of recessive state

Parameter	Notation	Value	Value	Value	Condition
Parameter	Notation	Min
V	Nom V	Max
V	Condition
Operating input voltage	VCAN_H	-12,0	+2,5	+12,0	Measured with respect to the individual ground of each CAN node
Operating input voltage	VCANL	-12,0	+2,5	+12,0
Differential input voltagea	VDiff	-3,0	0	+0,012	Measured at each CAN node connected to the medium
a The differential input voltage is determined by a combination of the recessive state output voltages of the individual CAN nodes present.Therefore,VDiffis approximately zero.	a The differential input voltage is determined by a combination of the recessive state output voltages of the individual CAN nodes present.Therefore,VDiffis approximately zero.	a The differential input voltage is determined by a combination of the recessive state output voltages of the individual CAN nodes present.Therefore,VDiffis approximately zero.	a The differential input voltage is determined by a combination of the recessive state output voltages of the individual CAN nodes present.Therefore,VDiffis approximately zero.	a The differential input voltage is determined by a combination of the recessive state output voltages of the individual CAN nodes present.Therefore,VDiffis approximately zero.	a The differential input voltage is determined by a combination of the recessive state output voltages of the individual CAN nodes present.Therefore,VDiffis approximately zero.

Figure B.2 shows the voltages VCANHand VCANLin their interdependency during recessive state. CISO 2024-All rights reserved ISO11898-2:2024(en) +12,00V- +11,88V- +11,00V- 0v+ Range of operating input voltage of VCAN_H 0,012v 0,5V(Normal mode) 0,4V |(Low power mode) 0,12 v 3,0V Range of VCAN_H for recessive reception -11,50V -12,00V- VCANH(MAX)input VCANH(MIN)input VCANL Figure B.2—Valid voltage range of VCAN_H for recessive state,when VCAN_Lvaries from minimum to maximum common mode range Table B.2shows the CAN interface voltage parameters for reception of dominant state. CISO 2024-All rights reserved Table B.2—Input voltage parameters for reception of dominant state

Parameter	Notationb	Value	Value	Value	Condition
Parameter	Notationb	Min.
[V]	Nom.
[V]	Max.
[V]	Condition
Common mode voltage	VCANH	-10,8	+3,5	+12,0	Measured with respect to the individual ground of each CAN node
Common mode voltage	VCANL	-12,0	+1,5	+10,8	Measured with respect to the individual ground of each CAN node
Differential voltagea	VDiff	+1,2	+2,0	+3,0	Measured at each CAN node connected to the medium
a Normal bus load range,no arbitration.
bThe minimum value ofVcAN_H is determined by the minimum value of VCAN_Lplus the minimum value of Vpif.The maximum value of VcANL is determined by the maximum value of VcAN_Hminus the minimum value of Vpif The bus load increases as CAN nodes are added to the medium by RpIFr.Consequently,Voi decreases.The minimum value of VDi determines the number of CAN nodes allowed to be connected to the medium.Also,the cable material,length and cross-section between the HS-PMA implementations,as well as connectors,impact the VDiffthat can be measured at the receiving HS-PMA’s input.	a Normal bus load range,no arbitration.
bThe minimum value ofVcAN_H is determined by the minimum value of VCAN_Lplus the minimum value of Vpif.The maximum value of VcANL is determined by the maximum value of VcAN_Hminus the minimum value of Vpif The bus load increases as CAN nodes are added to the medium by RpIFr.Consequently,Voi decreases.The minimum value of VDi determines the number of CAN nodes allowed to be connected to the medium.Also,the cable material,length and cross-section between the HS-PMA implementations,as well as connectors,impact the VDiffthat can be measured at the receiving HS-PMA’s input.	a Normal bus load range,no arbitration.
bThe minimum value ofVcAN_H is determined by the minimum value of VCAN_Lplus the minimum value of Vpif.The maximum value of VcANL is determined by the maximum value of VcAN_Hminus the minimum value of Vpif The bus load increases as CAN nodes are added to the medium by RpIFr.Consequently,Voi decreases.The minimum value of VDi determines the number of CAN nodes allowed to be connected to the medium.Also,the cable material,length and cross-section between the HS-PMA implementations,as well as connectors,impact the VDiffthat can be measured at the receiving HS-PMA’s input.	a Normal bus load range,no arbitration.
bThe minimum value ofVcAN_H is determined by the minimum value of VCAN_Lplus the minimum value of Vpif.The maximum value of VcANL is determined by the maximum value of VcAN_Hminus the minimum value of Vpif The bus load increases as CAN nodes are added to the medium by RpIFr.Consequently,Voi decreases.The minimum value of VDi determines the number of CAN nodes allowed to be connected to the medium.Also,the cable material,length and cross-section between the HS-PMA implementations,as well as connectors,impact the VDiffthat can be measured at the receiving HS-PMA’s input.	a Normal bus load range,no arbitration.
bThe minimum value ofVcAN_H is determined by the minimum value of VCAN_Lplus the minimum value of Vpif.The maximum value of VcANL is determined by the maximum value of VcAN_Hminus the minimum value of Vpif The bus load increases as CAN nodes are added to the medium by RpIFr.Consequently,Voi decreases.The minimum value of VDi determines the number of CAN nodes allowed to be connected to the medium.Also,the cable material,length and cross-section between the HS-PMA implementations,as well as connectors,impact the VDiffthat can be measured at the receiving HS-PMA’s input.	a Normal bus load range,no arbitration.
bThe minimum value ofVcAN_H is determined by the minimum value of VCAN_Lplus the minimum value of Vpif.The maximum value of VcANL is determined by the maximum value of VcAN_Hminus the minimum value of Vpif The bus load increases as CAN nodes are added to the medium by RpIFr.Consequently,Voi decreases.The minimum value of VDi determines the number of CAN nodes allowed to be connected to the medium.Also,the cable material,length and cross-section between the HS-PMA implementations,as well as connectors,impact the VDiffthat can be measured at the receiving HS-PMA’s input.

Figure B.3 and Figure B.4 show the voltages VCAN_H and VCAN_Lin their interdependency during dominant state according to Table B.3. Table B.3—Input voltage parameters for reception of dominant state during arbitration

Parameter	Notationa	Value	Value	Condition
Parameter	Notationa	Min.
[V]	Max.
[V]	Condition
Common mode voltage	VCAN_H	-10,8	+12,0	Measured with respect to the individual ground of each CAN node
Common mode voltage	VCANL	-12,0	+10,8	一
Differential voltage	VDiff	+1,2	+8,0	Measured at each CAN node connected to the medium
a The minimum value of VcAN_H is determined by the minimum value of VCAN_Lplus the minimum value of Vpif The maximum value of VCAN_Lis determined by the maximum value of VCAN_Hminus the minimum value of VDiff
The maximum value of Vpifis specified by the upper limit during arbitration plus aground shift of up to 3V.	a The minimum value of VcAN_H is determined by the minimum value of VCAN_Lplus the minimum value of Vpif The maximum value of VCAN_Lis determined by the maximum value of VCAN_Hminus the minimum value of VDiff
The maximum value of Vpifis specified by the upper limit during arbitration plus aground shift of up to 3V.	a The minimum value of VcAN_H is determined by the minimum value of VCAN_Lplus the minimum value of Vpif The maximum value of VCAN_Lis determined by the maximum value of VCAN_Hminus the minimum value of VDiff
The maximum value of Vpifis specified by the upper limit during arbitration plus aground shift of up to 3V.	a The minimum value of VcAN_H is determined by the minimum value of VCAN_Lplus the minimum value of Vpif The maximum value of VCAN_Lis determined by the maximum value of VCAN_Hminus the minimum value of VDiff
The maximum value of Vpifis specified by the upper limit during arbitration plus aground shift of up to 3V.	a The minimum value of VcAN_H is determined by the minimum value of VCAN_Lplus the minimum value of Vpif The maximum value of VCAN_Lis determined by the maximum value of VCAN_Hminus the minimum value of VDiff
The maximum value of Vpifis specified by the upper limit during arbitration plus aground shift of up to 3V.

CISO 2024-All rights reserved ISO11898-2:2024(en) +12,0V +11,0V 0V -7,0V -9,0V -10,8V -11,1V -12,0V Range of operating input voltage of VCAN_H 8,0V dominant reception 3,0V 1,2v 0,9V VCANL VCAN_H(MAX)input VCANH(MIN)input Figure B.3—Valid voltage range of VCAN_H for monitoring dominant state,when VCANLvaries from minimum to maximum common mode range during normal-power mode,arbitration free scenario CISO 2024-All rights reserved ISO11898-2:2024(en) +12,00VT +11,00V Range of VCAN_H for 8,0v dominant reception 0V- 1,15V -7,00V VCANL -10,85v -12,00v Fig ure B.4—Valid voltage range of VCAN_H for monitoring dominant state while the HS-PMA is not connected to the medium,when VCANL varies from minimum to maximum common mode range during low-power mode CISO 2024-All rights reserved ISO11898-2:2024(en) B.3 Expectations on a datasheet of an HS-PMA implementation The datasheet needs to state the maximum supported bit rate according to the bit time requirements given in Table 15,Table 16 and Table 17. The datasheet needs to state the supported arbitration bit rates for partial networking in case selective wake-up functionality is implemented. In case the implemented selective wake-up functionality is tolerant to frames in FBFF and FEFF,the maximum supported ratio of data bit rate and arbitration bit rate needs to be stated,as well as the absolute maximum data bit rate. The datasheet needs to state which of the functionalities classified as optional in this document are implemented in the particular HS-PMA implementation (e.g.extended bus load range,transmit dominant timeout,CAN activity filter time,etc.) B.4 Overview of optional features and implementation choices Table B.4 lists functional options that are specified in this document. Table B.4—Optional features and functions

No.	Option	Reference
1	Support of extended bus-load range	Table 5
2	Transmit dominant timeout function	Table 13
3	Support of parameter set A	Table 15
4	Support of parameter set B	Table 16
5	Support of parameter set C	Table 17
6	Support of extended maximum ratings for CAN_H and CAN_L	Table 2
7	Support of wake-up functionality	Table 19
8	Passive recessive single-ended output characteristics terminated	Table 18
9	Driver symmetry based on Vec(alternative 1)or driver symmetry based on Vrec〔alternative 2)	Table 12

In case the HS-PMA implementation implements low-power mode(s),then a wake-up mechanism according to Table 20 needs to be implemented.Each wake-up mechanism has options and alternatives,which are summarized in Table B.5,Table B.6,Table B.7 and Table B.8. Table B.5—Alternative timings within the wake-up features

No.	Alternative 1	Alternative 2	Alternative 3	Reference
1	CAN activity filter time,long	CAN activity filter time,short	CAN activity filter time,
long and CAN activity filter time,short	Table 20
2	Wake-up timeout,shorta	Wake-up timeout,long	No wake-up timeout	Table 20
3	CAN activity filter time,long	CAN activity filter time,short	CAN activity filter time,
long and CAN activity filter time,short	Table A.16
a Only applicable for legacy devices.	a Only applicable for legacy devices.	a Only applicable for legacy devices.	a Only applicable for legacy devices.	a Only applicable for legacy devices.

Table B.6—Options of the selective wake-up functions

No.	Option	Reference
1	Support of disabling DLC matching	5.5.5.8

CISO 2024-All rights reserved ISO11898-2:2024(en) Table B.7—Alternative for handling of CAN FD frames by the selective wake-up function

No.	Alternative 1	Alternative 2	Alternative 3	Reference
1	No tolerance
(not recommended for new designs)	Tolerance to CAN FD frames
with bit rate ratio of up to 1:4 or maximum 2 Mbit/s in data
phase	Tolerance to CAN FD frames
with bit rate ratio of up to 1:10 or maximum 5 Mbit/s in data phase	5.5.5.6

Table B.8—Alternatives for TXD dominant timeout function

No.	Alternative 1	Alternative 2	Alternative 3	Reference
1	No timeout	Timeout,shorta	Timeout,long	5.4.2
a Only applicable for legacy devices	a Only applicable for legacy devices	a Only applicable for legacy devices	a Only applicable for legacy devices	a Only applicable for legacy devices

CISO 2024-All rights reserved ISO11898-2:2024(en) Annex C (informative) PN physical layer modes Table C.1 provides a summary of features of PN physical layer implementations. Table C.1—PN physical layer features

| PN-capable FD-tolerant transceiver mode | End of frame detection for CAN FD frames(glitch filter- ing),from FDF=recessive to EOF,when selective wake-up is enabled | Bus wake-up detection | Frame error counting | Frame error counter value | tsilence functionality | |---|---|---|---|---|---| | Normal | Required when frame errorr counting active/not required when frame error counting inactive | WUF detec- tion required | Optional | Counting up/ down active or no change | Active or inactive | | Transition nor- mal to low-pow- er | Required when frame error counting active/not required when frame error counting inactive | WUF detec- tion required | Optional | Counting up/ down active or no change | Active or inactive | | Low-power and tsilence not expired and bus biasing active | Required | WUF detec- tion required | Required | Counting up/ down active | Active | | Low-power and tsilence expired | Inactive | WUP detec- tion required | Inactive | Set value to zero | Inactive | | Low-power and tsilence not expired and bus biasing inactive (from WUPto bus bias active) | Inactive | WUP detec- tion required | Inactive | No change | Active | | Transition low-power to normal | Required when frame error counting active/not required when frame error counting inactive | WUF detec- tion optional | Optional | Counting up/ down active or no change | Active or inactive |

CISO 2024-All rights reserved ISO11898-2:2024(en) Bibliography [1] ISO 16845-2,Road vehicles—Controller area network (CAN)conformance test plan —Part 2:High- speed medium access unit—Conformance test plan [2] CiA 601-4,CAN FD node and system design—Part 4:Signal improvement [3] CiA 612-2,CANXLguidelines and application notes—Part 2:PWM-coding implementation guideline CISO 2024-All rights reserved ICS 43.040.15 Price based on 64 pages ◎ ISO 2024 All rights reserved

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